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[TD][COLOR=#000080][B]library[/B][/COLOR] [COLOR=#0000ff]ieee[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]use[/B][/COLOR] [COLOR=#0000ff]ieee[/COLOR].[COLOR=#0000ff]std_logic_1164[/COLOR].[COLOR=#000080][B]all[/B][/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]entity[/B][/COLOR] footest1 [COLOR=#000080][B]is[/B][/COLOR] [COLOR=#000080][B]port[/B][/COLOR][COLOR=#000066]([/COLOR] Input_natural[COLOR=#000066]:[/COLOR] [COLOR=#000080][B]in[/B][/COLOR] [COLOR=#0000ff]natural[/COLOR] [COLOR=#000080][B]range[/B][/COLOR] [COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066];[/COLOR] Event[COLOR=#000066]:[/COLOR] [COLOR=#000080][B]out[/B][/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]end[/B][/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] footest[COLOR=#000066];[/COLOR][COLOR=#000080][B]architecture[/B][/COLOR] rtl [COLOR=#000080][B]of[/B][/COLOR] footest [COLOR=#000080][B]is[/B][/COLOR] [COLOR=#000080][B]signal[/B][/COLOR] Input[COLOR=#000066]:[/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]begin[/B][/COLOR] [COLOR=#000080][B]process[/B][/COLOR][COLOR=#000066]([/COLOR]Input_natural[COLOR=#000066])[/COLOR] [COLOR=#000080][B]begin[/B][/COLOR] Input [COLOR=#000066]<=[/COLOR] [COLOR=#000066]([/COLOR][COLOR=#000080][B]others[/B][/COLOR] [COLOR=#000066]=>[/COLOR] '[COLOR=#ff0000]0[/COLOR]'[COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR] Input[COLOR=#000066]([/COLOR]Input_natural[COLOR=#000066])[/COLOR] [COLOR=#000066]<=[/COLOR] '[COLOR=#ff0000]1[/COLOR]'[COLOR=#000066];[/COLOR] [COLOR=#000080][B]end[/B][/COLOR] foo[COLOR=#000066];[/COLOR] [COLOR=#008000][I]-- Instantiate an entity that contains the code you posted in your original posting[/I][/COLOR] [COLOR=#008000][I]-- Or simply include your code here. No matter which form you include you should[/I][/COLOR] [COLOR=#008000][I]-- get a binary file output from synthesis that is byte for byte identical.[/I][/COLOR][COLOR=#000080][B]end[/B][/COLOR] rtl[COLOR=#000066];[/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] footest2 [COLOR=#000080][B]is[/B][/COLOR] [COLOR=#000080][B]port[/B][/COLOR][COLOR=#000066]([/COLOR] Input[COLOR=#000066]:[/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR] Event[COLOR=#000066]:[/COLOR] [COLOR=#000080][B]out[/B][/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]end[/B][/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] foo[COLOR=#000066];[/COLOR][COLOR=#000080][B]architecture[/B][/COLOR] rtl [COLOR=#000080][B]of[/B][/COLOR] footest2 [COLOR=#000080][B]is[/B][/COLOR][COLOR=#000080][B]begin[/B][/COLOR] [COLOR=#008000][I]-- Instantiate an entity that contains the code you posted in your original posting[/I][/COLOR] [COLOR=#008000][I]-- Or simply include your code here. You will get different output results depending[/I][/COLOR] [COLOR=#008000][I]-- on which code you include here. Both of these will also be different than that[/I][/COLOR] [COLOR=#008000][I]-- produced by footest1.[/I][/COLOR][COLOR=#000080][B]end[/B][/COLOR] rtl[COLOR=#000066];[/COLOR]
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