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VHDL simple code vs for loop

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shaiko

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Will both of the codes below create identical logic ?

Code:
process is	
begin
	if reset = '1' then
		events <= ( others => '0' ) ;
	elsif input ( 0 ) /= default ( 0 ) then
		events ( 0 ) <= '1' ;
	elsif input ( 1 ) /= default ( 1 ) then
		events ( 1 ) <= '1' ;
	elsif input ( 2 ) /= default ( 2 ) then
		events ( 2 ) <= '1' ;
	end if ;
end process ;
Code:
process is
begin
	if reset = '1' then
		events <= ( others => '0' ) ;
	else
		for i in 0 to 2
		loop
			if input ( i ) /= default ( i ) then
				events ( i ) <= '1' ;
			end if ;
		end loop ;
	end if ; 
end process ;
 

K-J

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Will both of the codes below create identical logic ?

Code:
process is    
begin
    if reset = '1' then
        events <= ( others => '0' ) ;
    elsif input ( 0 ) /= default ( 0 ) then
        events ( 0 ) <= '1' ;
    elsif input ( 1 ) /= default ( 1 ) then
        events ( 1 ) <= '1' ;
    elsif input ( 2 ) /= default ( 2 ) then
        events ( 2 ) <= '1' ;
    end if ;
end process ;
Code:
process is
begin
    if reset = '1' then
        events <= ( others => '0' ) ;
    else
        for i in 0 to 2
        loop
            if input ( i ) /= default ( i ) then
                events ( i ) <= '1' ;
            end if ;
        end loop ;
    end if ; 
end process ;
No. The situation where multiple bits of 'input' are not set to the corresponding bit of 'default' will cause multiple bits of 'events' to be set to '1' in the for loop, but not in the 'if statement' version (Mentally set all bits of 'inputs' /= the appropriate bits of 'default').

Now you can argue that in your situation 'you know' that individual bits of 'inputs' will be mutually exclsuive, but unless they are provably so, you will get different logic. The only way to get this proof of exclusiveness is if the bits of 'input' come from something that truly is exclusive. If there is a provable mutual exclusiveness, then both forms will produce the same logic.

Kevin Jennings
 
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FvM

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No, not exactly due to the elsif chain. As long as the first condition is true, the second and third won't be checked. But I guess, it's unwanted. The exact equivalent looks like this:

Code:
process is	
begin
  if reset = '1' then
    events <= ( others => '0' ) ;
  else
    if input ( 0 ) /= default ( 0 ) then
      events ( 0 ) <= '1' ;
    end if;
    if input ( 1 ) /= default ( 1 ) then
      events ( 1 ) <= '1' ;
    end if;
    if input ( 2 ) /= default ( 2 ) then
      events ( 2 ) <= '1' ;
    end if ;
  end if;
end process ;
 
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shaiko

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The only way to get this proof of exclusiveness is if the bits of 'input' come from something that truly is exclusive. If there is a provable mutual exclusiveness, then both forms will produce the same logic
Will the synthesis tool even "bother" to see if the conditions are exclusive ?
 

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Will the synthesis tool even "bother" to see if the conditions are exclusive ?
Yes, if the input signals are originated from the same design.

But what's the problem you are behind? Either if the pathes are intended to be evaluated in parallel or mutual exlusive, your behavioral code can say it clearly.

A problem is brought up, if you mean the one and write the other. There's one thing, the synthesis tool definitely
can't: Guess, which code you meaned to write but actually didn't.
 

K-J

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Will the synthesis tool even "bother" to see if the conditions are exclusive ?
No, it won't bother to check at all, it will be inherent in the logic description. The (untested, not compiled, but close enough for someone to fix and test my claims) code is below. In 'footest1', the raw input is an integer. Something that is an integer can only have one value, each value is distinct, therefore they are mutually exclusive. The bits of the resulting std_logic_vector that are then the inputs to your code then must also be mutually exclusive. In 'footest2', the raw input is a std_logic_vector, there is no way for the synthesis tool to magically 'know' that the bits are mutually exclusive, because in fact there is no such guarantee.

Kevin Jennings

Code:
[LEFT][TABLE="class: vhdl syntaxHighlighter expand"]
[TR]
[TD="colspan: 2"]Code VHDL - [[COLOR=#226c22]expand[/COLOR]]
[/TD]
[/TR]
[TR="class: li1"]
[TD]12345678910111213141516171819202122232425262728293031
[/TD]
[TD][COLOR=#000080][B]library[/B][/COLOR] [COLOR=#0000ff]ieee[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]use[/B][/COLOR] [COLOR=#0000ff]ieee[/COLOR].[COLOR=#0000ff]std_logic_1164[/COLOR].[COLOR=#000080][B]all[/B][/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]entity[/B][/COLOR] footest1 [COLOR=#000080][B]is[/B][/COLOR] [COLOR=#000080][B]port[/B][/COLOR][COLOR=#000066]([/COLOR]   Input_natural[COLOR=#000066]:[/COLOR]  [COLOR=#000080][B]in[/B][/COLOR] [COLOR=#0000ff]natural[/COLOR] [COLOR=#000080][B]range[/B][/COLOR] [COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066];[/COLOR]   Event[COLOR=#000066]:[/COLOR] [COLOR=#000080][B]out[/B][/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]end[/B][/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] footest[COLOR=#000066];[/COLOR][COLOR=#000080][B]architecture[/B][/COLOR] rtl [COLOR=#000080][B]of[/B][/COLOR] footest [COLOR=#000080][B]is[/B][/COLOR]   [COLOR=#000080][B]signal[/B][/COLOR] Input[COLOR=#000066]:[/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]begin[/B][/COLOR]   [COLOR=#000080][B]process[/B][/COLOR][COLOR=#000066]([/COLOR]Input_natural[COLOR=#000066])[/COLOR]   [COLOR=#000080][B]begin[/B][/COLOR]      Input [COLOR=#000066]<=[/COLOR] [COLOR=#000066]([/COLOR][COLOR=#000080][B]others[/B][/COLOR] [COLOR=#000066]=>[/COLOR] '[COLOR=#ff0000]0[/COLOR]'[COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR]      Input[COLOR=#000066]([/COLOR]Input_natural[COLOR=#000066])[/COLOR] [COLOR=#000066]<=[/COLOR] '[COLOR=#ff0000]1[/COLOR]'[COLOR=#000066];[/COLOR]   [COLOR=#000080][B]end[/B][/COLOR] foo[COLOR=#000066];[/COLOR]    [COLOR=#008000][I]-- Instantiate an entity that contains the code you posted in your original posting[/I][/COLOR]   [COLOR=#008000][I]-- Or simply include your code here.  No matter which form you include you should[/I][/COLOR]   [COLOR=#008000][I]-- get a binary file output from synthesis that is byte for byte identical.[/I][/COLOR][COLOR=#000080][B]end[/B][/COLOR] rtl[COLOR=#000066];[/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] footest2 [COLOR=#000080][B]is[/B][/COLOR] [COLOR=#000080][B]port[/B][/COLOR][COLOR=#000066]([/COLOR]   Input[COLOR=#000066]:[/COLOR]  [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR]   Event[COLOR=#000066]:[/COLOR] [COLOR=#000080][B]out[/B][/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]end[/B][/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] foo[COLOR=#000066];[/COLOR][COLOR=#000080][B]architecture[/B][/COLOR] rtl [COLOR=#000080][B]of[/B][/COLOR] footest2 [COLOR=#000080][B]is[/B][/COLOR][COLOR=#000080][B]begin[/B][/COLOR]   [COLOR=#008000][I]-- Instantiate an entity that contains the code you posted in your original posting[/I][/COLOR]   [COLOR=#008000][I]-- Or simply include your code here.  You will get different output results depending[/I][/COLOR]   [COLOR=#008000][I]-- on which code you include here.  Both of these will also be different than that[/I][/COLOR]   [COLOR=#008000][I]-- produced by footest1.[/I][/COLOR][COLOR=#000080][B]end[/B][/COLOR] rtl[COLOR=#000066];[/COLOR]
[/TD]
[/TR]
[/TABLE]
[/LEFT]


---------- Post added at 20:11 ---------- Previous post was at 20:07 ----------

Code:
[LEFT][TABLE="class: vhdl syntaxHighlighter expand"]
[TR]
[TD="colspan: 2"]Code VHDL - [[COLOR=#226c22]expand[/COLOR]]
[/TD]
[/TR]
[TR="class: li1"]
[TD]12345678910111213141516171819202122232425262728293031
[/TD]
[TD][COLOR=#000080][B]library[/B][/COLOR] [COLOR=#0000ff]ieee[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]use[/B][/COLOR] [COLOR=#0000ff]ieee[/COLOR].[COLOR=#0000ff]std_logic_1164[/COLOR].[COLOR=#000080][B]all[/B][/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]entity[/B][/COLOR] footest1 [COLOR=#000080][B]is[/B][/COLOR] [COLOR=#000080][B]port[/B][/COLOR][COLOR=#000066]([/COLOR]   Input_natural[COLOR=#000066]:[/COLOR]  [COLOR=#000080][B]in[/B][/COLOR] [COLOR=#0000ff]natural[/COLOR] [COLOR=#000080][B]range[/B][/COLOR] [COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066];[/COLOR]   Event[COLOR=#000066]:[/COLOR] [COLOR=#000080][B]out[/B][/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]end[/B][/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] footest[COLOR=#000066];[/COLOR][COLOR=#000080][B]architecture[/B][/COLOR] rtl [COLOR=#000080][B]of[/B][/COLOR] footest [COLOR=#000080][B]is[/B][/COLOR]   [COLOR=#000080][B]signal[/B][/COLOR] Input[COLOR=#000066]:[/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]begin[/B][/COLOR]   [COLOR=#000080][B]process[/B][/COLOR][COLOR=#000066]([/COLOR]Input_natural[COLOR=#000066])[/COLOR]   [COLOR=#000080][B]begin[/B][/COLOR]      Input [COLOR=#000066]<=[/COLOR] [COLOR=#000066]([/COLOR][COLOR=#000080][B]others[/B][/COLOR] [COLOR=#000066]=>[/COLOR] '[COLOR=#ff0000]0[/COLOR]'[COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR]      Input[COLOR=#000066]([/COLOR]Input_natural[COLOR=#000066])[/COLOR] [COLOR=#000066]<=[/COLOR] '[COLOR=#ff0000]1[/COLOR]'[COLOR=#000066];[/COLOR]   [COLOR=#000080][B]end[/B][/COLOR] foo[COLOR=#000066];[/COLOR]    [COLOR=#008000][I]-- Instantiate an entity that contains the code you posted in your original posting[/I][/COLOR]   [COLOR=#008000][I]-- Or simply include your code here.  No matter which form you include you should[/I][/COLOR]   [COLOR=#008000][I]-- get a binary file output from synthesis that is byte for byte identical.[/I][/COLOR][COLOR=#000080][B]end[/B][/COLOR] rtl[COLOR=#000066];[/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] footest2 [COLOR=#000080][B]is[/B][/COLOR] [COLOR=#000080][B]port[/B][/COLOR][COLOR=#000066]([/COLOR]   Input[COLOR=#000066]:[/COLOR]  [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR]   Event[COLOR=#000066]:[/COLOR] [COLOR=#000080][B]out[/B][/COLOR] [COLOR=#0000ff]std_logic_vector[/COLOR][COLOR=#000066]([/COLOR][COLOR=#ff0000]0[/COLOR] [COLOR=#000080][B]to[/B][/COLOR] [COLOR=#ff0000]15[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066])[/COLOR][COLOR=#000066];[/COLOR][COLOR=#000080][B]end[/B][/COLOR] [COLOR=#000080][B]entity[/B][/COLOR] foo[COLOR=#000066];[/COLOR][COLOR=#000080][B]architecture[/B][/COLOR] rtl [COLOR=#000080][B]of[/B][/COLOR] footest2 [COLOR=#000080][B]is[/B][/COLOR][COLOR=#000080][B]begin[/B][/COLOR]   [COLOR=#008000][I]-- Instantiate an entity that contains the code you posted in your original posting[/I][/COLOR]   [COLOR=#008000][I]-- Or simply include your code here.  You will get different output results depending[/I][/COLOR]   [COLOR=#008000][I]-- on which code you include here.  Both of these will also be different than that[/I][/COLOR]   [COLOR=#008000][I]-- produced by footest1.[/I][/COLOR][COLOR=#000080][B]end[/B][/COLOR] rtl[COLOR=#000066];[/COLOR]
[/TD]
[/TR]
[/TABLE]
[/LEFT]
What the heck is up with this web site that nearly every time that I post code it gets collapsed into this one line garbage??? Makes me NOT want to use the syntax highlighter and 'code' tags
 
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shaiko

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Yeah,
It does happen sometimes...
 

alexan_e

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What the heck is up with this web site that nearly every time that I post code it gets collapsed into this one line garbage??? Makes me NOT want to use the syntax highlighter and 'code' tags
It is becasue you use SYNTAX tags inside CODE tags, in addition once you do that I can't fix it by editing your post because there are hundreds of format tags added and the code is beyond repair.

Use either CODE tags or SYNTAX tags but not one inside the other.
There is no problem to use the code tag in one part and syntax tag in another part of the same post.

Alex

---------- Post added at 03:31 ---------- Previous post was at 03:11 ----------

Actually I'm not sure what you are doing, I just tried syntax inside code tags
Code:
[syntax=vhdl]process is    
begin
    if reset = '1' then
        events <= ( others => '0' ) ;
    elsif input ( 0 ) /= default ( 0 ) then
        events ( 0 ) <= '1' ;
    elsif input ( 1 ) /= default ( 1 ) then
        events ( 1 ) <= '1' ;
    elsif input ( 2 ) /= default ( 2 ) then
        events ( 2 ) <= '1' ;
    end if ;
end process ;[/syntax]
And code tags inside syntax tags and I don't get the same problem

Code VHDL - [expand]
1
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3
4
5
6
7
8
9
10
11
12
[CODE]process is    
begin
    if reset = '1' then
        events <= ( others => '0' ) ;
    elsif input ( 0 ) /= default ( 0 ) then
        events ( 0 ) <= '1' ;
    elsif input ( 1 ) /= default ( 1 ) then
        events ( 1 ) <= '1' ;
    elsif input ( 2 ) /= default ( 2 ) then
        events ( 2 ) <= '1' ;
    end if ;
end process ;[/CODE]



I saw the same problem in your older posts too so I don't know what is wrong.
Can you post your code without any tags so I can test it?
 

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