vhdl signal assignment in process

[p11]

Any signal assignment becomes effective only when the process suspends. Until that moment, all signals keep their old values.
• Only the last assignment to a signal will be effectively executed. Therefore, it would make no sense to assign more than one value to a signal in the same process.

begin
process
begin

a<='1';

b<='0'

end process

in this case does the value be updated instantly .if no, then when will the value be updated ? i mean say if i connect an fpga and implement the program then does the port corresponding to a will get +5 v and that b gets 0v . is it ?? if yes then what does "Any signal assignment becomes effective only when the process suspends. Until that moment, all signals keep their old values " means ??plz cooperate.

 

[vGoodtimes]

Any signal assignment becomes effective only when the process suspends. Until that moment, all signals keep their old values.
• Only the last assignment to a signal will be effectively executed. Therefore, it would make no sense to assign more than one value to a signal in the same process.

It is useful to assign to a signal multiple times, though it is best not to abuse this language feature too much. Here is an example:

process (clk) is
begin
  if rising_edge(clk) then
    cnt <= cnt + 1; -- normally, the counter will always increment
    -- assume the process is longer, and the following occurs commonly*
    if some_event = '1' then
      cnt <= (others => '0'); -- in some cases, the counter should reset.
    end if;
    if reset = '1' then
      cnt <= (others => '0'); -- placing the reset at the end is convenient.
    end if;
  end if;
end process;

Now clearly the above code could be rewritten to avoid the overrides. For this very short example, it probably looks odd. But having a "default assignment" at the top and a placing the reset case last allows for convenient code that is still readable.

in this case does the value be updated instantly .if no, then when will the value be updated ? i mean say if i connect an fpga and implement the program then does the port corresponding to a will get +5 v and that b gets 0v . is it ?? if yes then what does "Any signal assignment becomes effective only when the process suspends. Until that moment, all signals keep their old values " means ??plz cooperate.

Basically, the processes describe logic circuits. The order the simulator runs each process is assumed to be unpredictable. This only matters if one process uses signals that are _instantly_ set in a second process. To deal with this, signals are not updated instantly. Instead, the next values are computed within each process. Once all triggered processes have been evaluated, then the values are assigned.

This is how hardware works -- each circuit is running at the same time as every other circuit and all logic is done in parallel.

 

[p11]

ok, but as i know that the process repeats infinite times unless and until it gets wait statement . is it correct ?? somewhrere else i have also read , that if the signal values in the sensitivity list of the process change then the process repeats .. plz explain me this 2 matter ..

 

[sharath666]

Both your points are correct..

 

[vGoodtimes]

p11, avoid using the process without sensitivity list + wait construct. While I'm not 100% sure it won't synthesize in very specific cases, I've never seen anyone use it outside of simulation-only code.

 

[p11]

if i use a process with a sensitivity list then for any change of the signals in the sensitivity list , the process repeats unlike the case where process without sensitivity repeats infinite times . am i right ?

- - - Updated - - -

begin
process
begin

a<='1';

wait for 10 ms;

b<='0'

end process

in this case b and a will get their values parallely , then how does the wait work???

 

[TrickyDicky]

The wait halts the process for 10 ms and allows the signals to be assigned their values.
Did you find a text book yet? Learning from a forum is going to be a terrible idea.

 

[p11]

thats what i want to knowsince the signal assignment to this different signals occur parallely so in this case that will occur parallely but after 10 ns ????

 

[TrickyDicky]

thats what i want to knowsince the signal assignment to this different signals occur parallely so in this case that will occur parallely but after 10 ns ????

Did you read a VHDL book yet? it has plenty of good examples with circuit diagram examples
Btw, your quesiton made little sense.