alexz
Full Member level 5

VHDL RTL question
It is not easy to describe the problem, but I will try.
I have a 16 bits latch, where it's output bus 16 bits is connected to the input of a 16 bits tri state buffer.
Both of the components are instantiated from lower level hierarchy.
The output of the tri state buffer is conected to a bidir 16 bits port.
I have got the following warning after the successful compilation using Quartus 2:
Warning: Removed fan-in from always-disabled I/O buffer TriStateBuffer:TSB|biDirPort[0] to tri-state bus PIN_DSP_BUS[0]~15
I have got the similar warning on every bit, 16 times.
I can also see on the RTL viewer that the bidir port (tri state buffer output) bit 15 and 14 are taken away to a second page of the viewer and connected togather to the bidir port again.
I do not understand why it happens and what it means.
It is not easy to describe the problem, but I will try.
I have a 16 bits latch, where it's output bus 16 bits is connected to the input of a 16 bits tri state buffer.
Both of the components are instantiated from lower level hierarchy.
The output of the tri state buffer is conected to a bidir 16 bits port.
I have got the following warning after the successful compilation using Quartus 2:
Warning: Removed fan-in from always-disabled I/O buffer TriStateBuffer:TSB|biDirPort[0] to tri-state bus PIN_DSP_BUS[0]~15
I have got the similar warning on every bit, 16 times.
I can also see on the RTL viewer that the bidir port (tri state buffer output) bit 15 and 14 are taken away to a second page of the viewer and connected togather to the bidir port again.
I do not understand why it happens and what it means.