Vhdl real vs Verilog real

[xlynx3]

Hi,

I'm trying VHDL real valued modeling of analog blocks (analog ports as VHDL real) for digital simulation purpose only.

I'm wondering that, is there any difference between Verilog real and VHDL real. I'm saying this because, the real valued modeling equivalance of VHDL real is shown as Verilog AMS wreal in some documents.

Any comments?

Thanks in advance & Best Regards..