vhdl real time clock code for spartan 3e family

pls anyone give idea for me to write the vhdl code for real time clock .
especially i dont no to set the clock frequency for spartan 3e family pls if anyone knows post the code :-?

check this link:
VHDL coding tips and tricks: Digital clock in VHDL

hi the above coding was helpful but i need to change the clock frequency how it was possible to set the frequency for spartan 3e XC3S100E

-------------------vhdl code for real time clock---------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity real_time is

Port ( clk, reset : in STD_LOGIC;
ca : out STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(0 to 6);
led : out STD_LOGIC_VECTOR(1 downto 0));
end real_time;

architecture Behavioral of real_time is
signal count : STD_LOGIC_VECTOR(24 downto 0);
signal s1:std_logic_vector(1 downto 0);
--signal s2:std_logic_vector(24 downto 0);
signal cth : std_logic_vector (3 downto 0);
signal clk_count,clk_count1 : STD_LOGIC;
SIGNAL dis1 : INTEGER RANGE 0 TO 10;
SIGNAL dis2 : INTEGER RANGE 0 TO 6;
SIGNAL dis3 : INTEGER RANGE 0 TO 5;
SIGNAL dis4 : INTEGER RANGE 0 TO 3;
SIGNAL led_count : std_logic_vector (1 downto 0);
--SIGNAL cth_count : std_logic_vector (1 downto 0);

begin

clk_count <= count (21);-- 1 SEC
clk_count1 <= count (21);-- 1 K
ca <= cth;
--scan_count <= count(9 downto 8);


--led(15) <= count (10);
process(clk,reset)---clk division
begin
if (reset='1') then
count <= (others => '0');
elsif (clk='1' and clk'event) then

if(count = "1111111111111111111111111")then
count <= (others => '0');
else
count <= count + 1;
s1 <= count(8 downto 7);
end if;

end if;
end process;

process(reset,clk_count)
begin
if(reset = '1')then

dis1 <= 0;
dis2 <= 0;
dis3 <= 0;
dis4 <= 0;
elsif(rising_edge (clk_count))then
if(dis1 = 9)then--"1010")then
dis1 <= 0;
if(dis2 = 5) then
dis2 <= 0;
if(dis3 = 4) then
dis3 <= 0;
if(dis4 = 2) then
dis4 <= 1;
else
dis4 <= dis4 + 1;
end if;
else
dis3 <= dis3 + 1;
end if;
else
dis2 <= dis2 + 1;
end if;
else
dis1 <= dis1 + 1;

end if;

end if;

end process;

process(clk, reset,dis1,dis2,dis3, dis4,cth,s1)

begin
if(reset = '1')then

y <= "1111110";
elsif(clk'event and clk = '1') then
if (s1="00")then
cth<="0001";
y<="1111110";
elsif (s1="01")then
cth<="0010";
y<="1111110";
elsif (s1="10")then
cth<="0100";
y<="1111110";
elsif (s1="11")then
cth<="1000";
y<="1111110";
end if;
if (cth = "0001") THEN
case dis1 is
--when 1 => y <= "1111110";
when 1 => y <= "0110000";
when 2 => y <= "1101101";
when 3 => y <= "1111001";
when 4 => y <= "0110011";
when 5 => y <= "1011011";
when 6 => y <= "1011111";
when 7 => y <= "1110000";
when 8 => y <= "1111111";
when 9 => y <= "1111011";
when others=> null;
end case;

ELSif (cth = "0010")THEN
case dis2 is
when 1 => y <= "0110000";
when 2 => y <= "1101101";
when 3 => y <= "1111001";
when 4 => y <= "0110011";
when 5 => y <= "1011011";
when others=> null;
end case;


ELSif (cth= "0100")THEN
case dis3 is
--when 0 => y <= "1111110";
when 1 => y <= "0110000";
when 2 => y <= "1101101";
when 3 => y <= "1111001";
when 4 => y <= "0110011";

when others=> null;
end case;

ELSif (cth = "1000")THEN
case dis4 is
when 0 => y <= "1111110";
when 1 => y <= "0110000";
when 2 => y <= "1101101";
when others=> null;
end case;
end if;
end if;

end process;
process(reset, clk_count1,led_count)
begin
if (reset = '1') then
led_count<="01";
elsif ( rising_edge(clk_count1)) then
if( led_count= "11")then--"1010")then
led_count <= "01";
else
led_count <= led_count + 1;

case led_count is

when "01" => led <= "00";
when "10" => led <= "11";
when others => null;
end case;
end if;
end if;

end process;
end Behavioral;

Nice work buddy.

you can check the real time clock code on my blog: VHDL codes

and video on my channel: YouTube - Real time Clock (RTC) in VHDL (Altera DE1 board)