VHDL question 2 - how to get codes together in one code

entity Adder_1bit is
  port
  (
    a : in std_logic;
    b : in std_logic;
    cin : in std_logic;
    y : out std_logic;
    cout : out std_logic
  );
end entity Adder_1bit;

entity Adder_4bit is
  port
  (
    a : in std_logic_vector(3 downto 0);
    b : in std_logic_vector(3 downto 0);
    cin : in std_logic;
    y : out std_logic_vector(3 downto 0);
    cout : out std_logic
  );
end entity Adder_4bit;

architecture structural of Adder_4bit is
  component Adder_1bit
    port
    (
      a : in std_logic;
      b : in std_logic;
      cin : in std_logic;
      y : out std_logic;
      cout : out std_logic
    );
  end component Addr_1bit;

  signal carries : std_logic_vector(2 downto 0);
begin
  a0 : Adder_1bit port map (a => a(0), b => b(0), y => y(0), cin => cin,        cout => carries(0) );
  a1 : Adder_1bit port map (a => a(1), b => b(1), y => y(1), cin => carries(0), cout => carries(1) );
  a2 : Adder_1bit port map (a => a(2), b => b(2), y => y(2), cin => carries(1), cout => carries(2) );
  a3 : Adder_1bit port map (a => a(3), b => b(3), y => y(3), cin => carries(2), cout => cout );
end architecture structural;

entity adder_16bit is
  port
  (
    a : in std_logic_vector(15 downto 0);
    b : in std_logic_vector(15 downto 0);
    y : in std_logic_vector(15 downto 0);
  );

architecture rtl of some_entity is
  signal a_l : signed(a'range);
  signal b_l : signed(b'range);
  signal y_l : signed(y'range);
begin
  a_l <= signed(a);
  b_l <= signed(b);

  y_l <= a_l + b_l;

  y <= std_logic_vector(y_l);
end architecture rtl;