entity comparator_TestBench is
end comparator_TestBench;
architecture Stimulus of comparator_TestBench is
-- signal s_notClock50Mhz : std_logic;
signal s_hexDraft, s_hexReal : std_logic_vector(6 downto 0);
signal s_hexPosition : std_logic_vector(1 downto 0);
signal s_newHex : std_logic_vector(6 downto 0);
signal s_newHexPosition : std_logic_vector(1 downto 0);
begin
uut : entity work.comparator(Behav) -- Error in this line
port map(
-- notClock50Mhz => s_notClock50Mhz,
hexDraft => s_hexDraft,
hexReal => s_hexReal,
hexPosition => s_hexPosition,
newHex => s_newHex,
newHexPosition => s_newHexPosition
);