VHDL, Quartus II - Error: formal port or parameter must have actual or default value

[newbie99]

I am getting the following two errors: Error (10346): VHDL error at comparator_TestBench.vhd(17): formal port or parameter "beginGame" must have actual or default value

Error (10784): HDL error at comparator.vhd(8): see declaration for object "beginGame"

and both are related to assigning a default value for beginGame in my comparator.vhd file:

entity comparator is
port(   
        beginGame               : in std_logic; -- Error in this line
        hexDraft, hexReal   : in std_logic_vector(6 downto 0);
        hexPosition             : in std_logic_vector(1 downto 0);
        newHex                  : out std_logic_vector(6 downto 0);
        newHexPosition          : out std_logic_vector(1 downto 0));
end comparator;


architecture Behav of comparator is
    signal s_hexPosition : std_logic_vector(1 downto 0);

begin 



comp : process(hexDraft, hexReal, hexPosition, s_hexPosition)
begin

    if(beginGame = '1') then 
        if((hexDraft(0) = '0' and hexReal(0) = '0') or (hexDraft(1) = '0' and hexReal(1) = '0') or (hexDraft(2) = '0' and hexReal(2) = '0')
        or (hexDraft(3) = '0' and hexReal(3) = '0') or (hexDraft(4) = '0' and hexReal(4) = '0') or (hexDraft(5) = '0' and hexReal(5) = '0')
        or (hexDraft(6) = '0' and hexReal(6) = '0')) then
            if(hexPosition = "00") then
                s_hexPosition <= "10";
            elsif(hexPosition = "01") then
                s_hexPosition <= "11";
            elsif(hexPosition = "10") then
                s_hexPosition <= "00";
            else
                s_hexPosition <= "01";
            end if;
        else
            s_hexPosition <= hexPosition;
        end if;
    end if;
    newHexPosition <= s_hexPosition;
    newHex <= hexDraft;
end process;

end Behav;

and this's the part giving me an error in my comparator_TestBench.vhd file, which depends on my comparator.vhd

entity comparator_TestBench is
end comparator_TestBench;

architecture Stimulus of comparator_TestBench is

    -- signal   s_notClock50Mhz         : std_logic;
    signal  s_hexDraft, s_hexReal   : std_logic_vector(6 downto 0);
    signal  s_hexPosition               : std_logic_vector(1 downto 0);
    signal  s_newHex                    : std_logic_vector(6 downto 0);
    signal  s_newHexPosition            : std_logic_vector(1 downto 0);

begin 

        uut : entity work.comparator(Behav) -- Error in this line
            port map(
--              notClock50Mhz   => s_notClock50Mhz,
                hexDraft            => s_hexDraft,
                hexReal         =>  s_hexReal,
                hexPosition     => s_hexPosition,
                newHex          => s_newHex,
                newHexPosition  => s_newHexPosition
            );

I'm using altera DE2-115 board and Quartus II software
Any advice/ suggestions would be much appreciated.

 

[FvM]

Isn't the error message pretty clear? You are missing to assign an actual value to parameter "beginGame" which is then undefined in the instantiated component.

Solutions are:
assign a value in the port map, e.g.

beginGame => '1',

or define a default value in the port declaration, which will be used if no actual value is given

beginGame     : in std_logic := '1';

 

[newbie99]

Isn't the error message pretty clear? You are missing to assign an actual value to parameter "beginGame" which is then undefined in the instantiated component.

Solutions are:
assign a value in the port map, e.g.

beginGame => '1',

or define a default value in the port declaration, which will be used if no actual value is given

beginGame     : in std_logic := '1';

Thanks FvM, this solved the error. Yes, you're right it's pretty obvious.