VHDL program for d flipflop and its test bench waveform

[ambar686]

please post the vhdl program for d flip-flop. and also the test bench waveform(only the waveform, not its programming).

i have uploaded the test bench waveform of d flip flop, how to check if it is right?

 

[electroM]

Depending upon design check it's working. check for the input signal what output you are getting.

- - - Updated - - -

what u needed may be found here:
http://esd.cs.ucr.edu/labs/tutorial/#flip-flops

 

[ambar686]

her is my code, by using this code, i have got the waveform.. is the waveform right??

entity dff is
Port ( D: in std_logic;
CLK : in std_logic;
Q : out std_logic;
QN : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process (CLK)
begin
if (rising_edge(CLK)) then
Q <= D;
QN <= NOT D;
end if;
end process;
end Behavioral;

 

[Port Map]

the code is true, but in simulation, D toggles faster than Clk, and D changes near the rising edge of clk. its better to D be stable around Clk rising edges.

 

[aruipksni]

the code is true, but in simulation, D toggles faster than Clk, and D changes near the rising edge of clk. its better to D be stable around Clk rising edges.

you might have a setup/hold violations :
try run the following code :

[SYNTAX=VHDL]
library ieee;
use ieee.std_logic_1164.all;

entity dff is
  generic 
  (
    TS : time := 1 nS;
	TH : time := 1 ns
  );           -- size of memory
  port (
    Clk             : in std_logic;
    D               : in std_logic; 
	Q               : out std_logic := '0';
	Qn              : out std_logic := '1'
	);
  end entity;
	
architecture rtl of dff is

signal hold_is_good : std_logic := '1'; 
signal qq : std_logic := '0';
signal qqn : std_logic := '1';

begin
  
  flip_flop : PROCESS (clk)
 BEGIN
   
 IF (clk'EVENT AND clk='1') THEN  -- on clock rising edge..  
  if (d'STABLE(Ts)) THEN
    qq  <= d; 
    qqn <= not d;  -- ..set q output..
  else
    qq <= 'X';     -- ..otherwise, set q unknown
	qqn <= 'X'; 
    ASSERT false REPORT "FF: Data setup violation"
    SEVERITY error;
  end if;
 ELSE
  qq <= qq;                         -- ..otherwise, no change in q
  qqn <= qqn;
 END IF;
END PROCESS flip_flop;

process(hold_is_good,qq,qqn) is

begin

if (hold_is_good = '1') then
  q <= qq;
  qn <= qqn;
else
  q <= 'X';
  qn <= 'X';
end if;

end process;

flip_flop_h : PROCESS
 BEGIN
  -- wait until a clock rising edge
  WAIT UNTIL (clk'EVENT AND clk='1');
  WAIT FOR (TH);                     -- wait hold time
  -- check d has been stable for time Thld
  
  IF (d'STABLE(TH)) THEN    
   hold_is_good <= '1';                            -- ..set q output to d..  
  ELSE
   hold_is_good <= '0';                           -- ..otherwise, set q unknown
   ASSERT false REPORT "FF: Data hold violation"
   SEVERITY error;
  END IF;
  
END PROCESS flip_flop_h;
 
end rtl;

-----------------
entity  tb_dff is

end entity ;
--------------------------------------------------------------------------------


architecture Bhv of tb_dff is
  -----------------------------
  -- Port Signals 
  -----------------------------
constant TS  : time := 1 ns;
constant TH  : time := 1 ns;
signal   Clk : std_logic := '1';
signal   D   : std_logic := '0';
signal   Q   : std_logic;
signal   Qn  : std_logic;

  
begin  -- architecture Bhv

  -----------------------------
  -- component instantiation 
  -----------------------------
  dff_INST: entity work.dff
   generic map (
      TS => TS,
      TH => TH)
   port map (
      Clk => Clk,
      D   => D,
      Q   => Q,
      Qn  => Qn);

  Clk <= not Clk after 5 ns;
  StimuliProcess : process
  begin
   D <='0';
   REPORT "DFF : GOOD SCENARIO :";
   REPORT "===================";
   wait until rising_edge(Clk);
   wait until rising_edge(Clk);
   wait until rising_edge(Clk);
   wait until rising_edge(Clk);
   wait until rising_edge(Clk);
   wait for 8 ns;
   D <='1';
   wait until rising_edge(Clk);
   wait for 2 ns;
   D <= '0';
   --------------------------
   REPORT "DFF : setup violation scenario SCENARIO";
   REPORT "=======================================";
   wait until rising_edge(Clk);
   wait for 9.5 ns;
   D <='1';
   wait until rising_edge(Clk);
   wait for 2 ns;
   D <= '0';
   wait until rising_edge(Clk);
   wait until rising_edge(Clk);
   --------------------------
   REPORT "DFF : hold violation scenario SCENARIO";
   REPORT "======================================";
   wait until rising_edge(Clk);
   wait for 8 ns;
   D <='1';
   wait until rising_edge(Clk);
   wait for 0.5 ns;
   D <= '0';
   wait until rising_edge(Clk);
   wait until rising_edge(Clk);
   ----------------------------
   REPORT "DFF : hold and setup violation scenario SCENARIO";
   REPORT "================================================";
   wait until rising_edge(Clk);
   wait for 9.5 ns;
   D <='1';
   wait until rising_edge(Clk);
   wait for 0.5 ns;
   D <= '0';
   -----------------------------
   wait until rising_edge(Clk);
   wait until rising_edge(Clk);
   wait;
  end process StimuliProcess;
  
end architecture Bhv;


[/SYNTAX]

 

[ambar686]

what i have ran , i have uploaded the code and it is simulated properly and i have got the waveform, now my question is that-- Is the waveform right what i have got???

 

[aruipksni]

what i have ran , i have uploaded the code and it is simulated properly and i have got the waveform, now my question is that-- Is the waveform right what i have got???

from first sight it doesn't look good, but mabee you are trying to fool me so you are using slow clok, and improper resoultion so it might be actually good.
whay don't you replace my stimuly with your waveform stimuly , change TS,TH to your needs, and see if it's good ?

 

[ads-ee]

ambar686,

The waveform looks very wrong, with the clk with pulse widths that change from cycle to cycle and the data transitioning at the rising edge of the clock. Do you understand the concept of setup and hold time? Maybe you missed the lecture on that?