VHDL Problem, please some help, it's just a division

[juanma21]

I can't finish my code, there's something I'm missing:

Using VHDL, design a circuit which will produce
1. Q = INT(Y/X) and R = Remainder of Y/X
2. Let Y be a 8-bit unsigned, and X=4-bit unsigned.
3. Your design should have an error signal (active high) if X=0.

This is my code:

-- Define Libraries
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;

-- Define input and output signals
Entity last is
port(y: in std_logic_vector(7 downto 0);
x:in std_logic_vector(3 downto 0);
quotut std_logic_vector(7 downto 0);
remainut std_logic_vector(3 downto 0);
start: in std_logic;
done,error: out std_logic);
End entity last;


-- define internal signals --
process(x,y,start,ps,py,px,pq,prem,pError,pDone)
begin
-- define default outputs
ns <= ps;
ny <= py;


case ps is
when Sstart=>
if(start='0') then ns <= Sstart; else ns <= SReset;
when Sreset =>
nError <= '0'; nDone <= '0';
nx <= x; ny <= y; nq <= "00000000"; nrem <= "0000";
if(x="0000") then
nerror <= '1';
ns <= Sstart;
else ns <= SLoop;
when SLoop=>
ny <= py – "0000"&px;
ny_lt_0 = {logic to determine if ny < 0};
if(ny_lt_0 = '0') then
nq <= pq + 1;
ns <= SLoop;
else ns <= SDone;
When SDone =>
nrem <= py + "0000"&px;
nDone <= '1';
ns <= Sstart;
When others => ns <= Sreset;
End case;
End process;


Thank you very much!!

 

[flanix]

you can use 'case statement' and subtration.

 

[juanma21]

Thank you!

The way is written is the way that have to be done, it´s just when I compile, it doesn´t work and I don´t know why.

I´m not very good with VHDL, until now all the problems were easier and could solve them, but not this one. I think I'm missing the architecture part and the H logic part. I'm not sure.

If you could give me a hand??

 

[flanix]

sure
if i konw, i can give you a favour.

give a email address.

i will give you some useful information.