VHDL Parameterized GENERIC for port size declaration?

[legendbb]

I was working on some library component.

To make the module generic, signals and ports have variable size, defined by generic at preprocessing time.

It assume it's OK if I have the math inside STD_LOGIC_VECTOR((cSOME_GENERIC - A + B - C) DOWNTO 0);

But the code looks messy, I try to redefine the size derivation as another generic to clean up (ie. (cDERIVED_GENERIC : integer := A+B+C). But it doesn't seem to work.

What's the right technique for doing this in VHDL?

Regards,

 

[TrickyDicky]

Your origional method was correct for VHDL '93 - because you cannot use generics to define other generics.
In the 2008 version of VHDL, you can do what you're trying - but only the newest version of vivado supports it (the new versions of quartus will support it when it gets released soon).

 

[legendbb]

Your origional method was correct for VHDL '93 - because you cannot use generics to define other generics.
In the 2008 version of VHDL, you can do what you're trying - but only the newest version of vivado supports it (the new versions of quartus will support it when it gets released soon).

Thanks a lot for your prompt reply, I quickly tried in Vivado 2015.1; Not able to make it to pass synthesis.

BTW, parameter in Verilog allows parameter to be defined by another parameter; which might serve as my alternative for now.

 

[TrickyDicky]

IIRC, Vivado 2015.1 supposrts this feature of VHDL 2008 if you change the setting