VHDL package and Modelsim

[ustinoff]

Hello. In my top level entity i use package for create an array of std_logic_vector and this array is my output data type (output buses are this array). When i try to simulate it by using Modelsim i watch only input ports in "Wave" window (they have standart std_logic/std_logic_vector types) and don't see output ports (they are array of std_logic_vector from package). What do i have to do to watch my output ports?

I invoke Modelsim by using script:

vlib work
vmap work
vcom PackageUnit.vhd
vcom AddOnUnit1.vhd
vcom AddOnUnit2.vhd
vcom TopLevelUnit.vhd
vsim -novopt work.TopLevelUnit
add wave TopLevelUnit

And Modelsim compiled all sources correctly.

 

[barry]

impossible to say without seeing your code.

 

[ustinoff]

impossible to say without seeing your code.

I found my signals in "Object" window

 

[CataM]

I found my signals in "Object" window

And is there the output signal listed?

 

[ustinoff]

And is there the output signal listed?

Yes. I added output signal (they have array type) from "Object" window and it works correctly.

 

[ads-ee]

This line

add wave TopLevelUnit

I've found does not necessarily add arrays to the wave window. Never looked into why Modelsim does this, but I've noticed this over the years. I usually write scripts to add all the signals I want in the wave window, which is run a soon as the simulation is loaded. I normally edit that file and delete/rerun the file when I updated the wave window. I've run across so many GUI bugs (crashing the simulator) over the years with Modelsim and now Vivado simulators that I avoid using the GUI to add anything to the waveform viewers.