ustinoff
Member level 2
Hello. In my top level entity i use package for create an array of std_logic_vector and this array is my output data type (output buses are this array). When i try to simulate it by using Modelsim i watch only input ports in "Wave" window (they have standart std_logic/std_logic_vector types) and don't see output ports (they are array of std_logic_vector from package). What do i have to do to watch my output ports?
I invoke Modelsim by using script:
And Modelsim compiled all sources correctly.
I invoke Modelsim by using script:
Code:
vlib work
vmap work
vcom PackageUnit.vhd
vcom AddOnUnit1.vhd
vcom AddOnUnit2.vhd
vcom TopLevelUnit.vhd
vsim -novopt work.TopLevelUnit
add wave TopLevelUnit
And Modelsim compiled all sources correctly.