Being working with ASIC for over 5 years, maybe I can offer a better advice on VHDL and Verilog.
If you are working at the top abstraction level where you work with functional simulation, modelling and RTL development, either VHDL or Verilog, there is strictly no difference. It depends on your experience in "thinking" and interpreting digital hardware in the logical manner.
If you work with Cadence Silicon Ensemble or NanoEncounter for Floorplan, Place-and-Route, you have to generate your gate-level netlist in Verilog from Synopsys or other logic synthesis tool. This is because Cadence, due to commercial reason as Cadence owns Verilog and supports its own SystemVerilog programme, designers are quite forced to stick with Verilog.
If you use other tools, such as MentorGraphics, TI Pyramid, etc, you can export your gate-level netlist in VHDL.
Personally I think it is easier to write testbenches with Verilog. It has better functions in reading testvectors.
There is problem in Verilog. Because it is frequent in many aspects to use Wire and Reg, if you encounter a hardware design where high-speed bus is required, synthesis tool can specify it as strong logic 1 or logic 0 signal, which is practically and realistically untrue because high-speed bus signals are almost so weak and close to switching threshold that it is quite like a triangle or sawtooth or distorted.
This is not the case with VHDL. With its strict and well-organised standard logic vectors with 9 defined levels, it resolves this issue that Verilog can only pray the hardware will work after tape-out.
Verilog is very much like C lang. Therefore it lacks rules to confine how a good RTL description should be styled. VHDL has strict rules to make sure that ASIC designers using VHDL will learn the right way from the beginning.
I think I have given my fair share on VHDL and Verilog.
Two things to add: US Defence Research DARPA uses only VHDL for defence projects. Perhaps it might be a hint that VHDL is a more robust HDL to use.
ChipIdea, a very strong multimedia ASIC company, selected by Microsoft to design the hardware for XBOX 360, uses VHDL and no Verilog.
Europe uses VHDL partly because the US Defence Research DARPA uses VHDL. Indications like such is quite clear that VHDL has reasons for very important roles above Verilog.