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VHDL or labview? which one is better

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Apr 22, 2011
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Hello i am new with programming FPGA's. I have started learning VHDL and i have a few projects in mind. While i was studying on vhdl a friend of mine told mw there is a program called labview that converts codes directly to VHDL. So in this case is it unnecessary to learn VHDL? Can everything be done using labview, and can this programming method then i graduate and start working in the industry? I will be very happy if someone saves me from this confusion.

1. Limited support for constants

* Non-synthesisable math functions unavailiable to operate on constants (eg log2(x))

* Functions with constant only inputs are seen to have variable outputs to the LabVIEW error checker, eg indexing an array with the output of 1+1 will cause an unconstrained array error.

* SubVI controls cannot be defined as constants, thus for example, using a control to index an array will also cause an unconstrained array error.

VHDL includes several non-synthesizable functions in the ieee.math_real library (amongst others). Complex user functions can be written that are interpreted at compile time to generate constants such as LUT values.

E.G, the following can be used to find the number of bits required to represent a given unsigned number.

function bits(arg:NATURAL) return NATURAL is

return INTEGER(ceil(log2(real(arg))));

end bits;

2. No parallel loops on FPGA target VIs

I was particularly surprised by the inability to declare parallel instances of the same function without copy/paste N-times. What seems natural to me in LabVIEW is to declare a parallel loop with N and P connected to the same constant, then so long as there are no data dependencies between iterations it should work. Parallel loops are unsupported in LabVIEW FPGA, where they would be very beneficial.

In VHDL the Generate construct is almost an exact match the LabVIEW parallel loop.

parallel_counter: for i in clear'range generate

process(clk, reset)

variable count : unsigned(output(i)'range);


if reset='1' then

count := (others<='0');

elsif rising_edge(clk) then

if clear(i) = '1' then

count := (others<='0');


count := count + 1;

end if;

end if;

output(i) <= count;

end process;

end generate;

3. No support for arrays >1D

VHDL supports ND arrays of bits however LabVIEW FPGA only supports operations on 1D arrays.

-- unconstrained 2d vector type

-- unconstrained 2d vector type in VHDL

type std_logic_2d is array(integer range <>, integer range <>) of STD_LOGIC;
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