VHDL - ModelSim - "Read past end of file" problem

[vtomic85]

Hi!

I want to read two integer values from a .txt file named "entry.txt", which is located in the project folder, with all of the .vhd files.

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Code VHDL - [expand]
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-- ...
variable inline : line;
file inputFile : text open read_mode is "entry.txt";
variable mynum: integer;
variable stdmynum: std_logic_vector (N-1 downto 0);
-- ...
readline(inputFile,inline);
read(inline,mynum);
stdmynum:= std_logic_vector(to_signed(mynum, stdmynum'length));
mem(0) := stdbroj;
readline(inputFile,inline);
read(inline,mynum);
stdmynum:= std_logic_vector(to_signed(mynum, stdmynum'length));
mem(1) := stdbroj;
-- ...

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When I start the simulation, I get a fatal error: "TEXTIO: Read past end of file "entry.txt"", in the line with the first readline command. My file contains two integers (one in the first line and the other one in the second line), and in the code you can see that I try to read two integers and nothing else.
What could be the problem?

 

[std_match]

Do you have the "end of line" sequence (hex 0a for unix/linux, hex 0d 0a for Windows) after the second number?
Some editors allow you to create files with "end of line" missing from the last line.
Unix/linux editor "vi" does not allow that.