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VHDL Model of RAM Module

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MRLL

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Hi,

I've only been using VHDL for a few months now, and i'm currently working on a RAM module in which the contents of the memory are initially loaded from a file. The module has 5 address lines, 8-birectional data lines, an active low enable, and a read/write select input.

At the moment, i've got to a stage were some sort of value seems to be read from the text value, however, the output always displays the last value in my 32 value, 8-bit array. This would suggest there's a problem with the addressing, but i can't seem to find the issue. Below is my code:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;


entity memory is
port(	enable		:in std_logic;
	RW		:in std_logic;
	addr		:in std_logic_vector(4 downto 0);
	data		:inout std_logic_vector(7 downto 0)
);
end memory;





architecture behaviour1 of memory is

signal data_out :std_logic_vector (7 downto 0);
type ram_type is array (0 to 31) of std_logic_vector(7 downto 0);
signal temp_ram: ram_type;					-- internal version of ram

begin	
			   
-- Tri-State Buffer control
data <= data_out when (enable = '1') else (others=>'Z');

-- Memory Write Block
process (RW, enable)
begin
if RW = '1' and enable = '0' then
temp_ram(conv_integer(addr)) <= data;
end if;
end process;

-- Memory Read Block
process (RW, enable)
begin
if RW = '0' and enable = '0' then
data_out <= temp_ram(conv_integer(addr));
end if;
end process;

end behaviour1;




entity memory_testbench is

end memory_testbench;





architecture testbench_1 of memory_testbench is
file loaddata: text;
-- signals
signal t_enable	:std_logic := '0';
signal t_RW	:std_logic := '0';
signal t_data	:std_logic_vector(7 downto 0);
signal t_wrdata	:std_logic_vector(7 downto 0);
signal t_redata	:std_logic_vector(7 downto 0);
signal t_addr	:std_logic_vector(4 downto 0);

-- components
component memory
port (
	enable	: in std_logic;
	RW	: in std_logic;
	addr	: in std_logic_vector(4 downto 0);
	data	: inout std_logic_vector(7 downto 0)
	);
end component;

begin

-- Device under test: memory

dut_1 : memory
	port map (
		enable => t_enable ,
		RW => t_RW ,
		addr => t_addr ,
		data => t_data);	

-- Test stimulus
t_data <= t_wrdata when t_RW='1' and t_enable='0';  
t_redata <= t_data when t_RW='0' and t_enable='0'; 



vectors : process
variable advalue: std_logic_vector(7 downto 0);
variable adline: line;

begin
file_open(loaddata,"C:\Users\Luke\Documents\loaddata.txt",read_mode);
while not endfile(loaddata) loop
readline(loaddata,adline);
read(adline,advalue);
end loop;

t_enable <= '0';
t_RW <= '1';
t_addr <= (t_addr'range => '0');
t_wrdata <= advalue;
wait for 100 ns;

t_enable <= '0';
t_RW <= '0';
t_addr <= t_addr + '1';
t_wrdata <= advalue;
wait for 100 ns;

t_enable <= '0';
t_RW <= '1';
t_addr <= t_addr + '1';
t_wrdata <= advalue;
wait for 100 ns;

t_enable <= '1';
t_RW <= '1';
t_addr <= t_addr + '1';
t_wrdata <= advalue;
wait for 100 ns;

wait;


end process vectors;

-- writes to standard output

results_to_screen: process (t_RW, t_enable, t_addr, t_data)
	variable Results : line;
	variable qi : integer;
begin
	report "Signal t_data is " & t_RW'image(t_RW) & " at time " & time'image(now);
	write(Results,Now);
	write(Results,' ');
	write(Results,t_enable);
	write(Results,t_RW);
	write(Results,t_addr);
	write(Results,t_data);
	write(Results,' ');
	writeline(output,Results);

end process results_to_screen;

end testbench_1;
Any help would be greatly appreciated.

Thanks.
 

FvM

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Code:
while not endfile(loaddata) loop
readline(loaddata,adline);
read(adline,advalue);
end loop;
If there is more than one data line in your file, it's ignored except for the last one that's stored in advalue. So the observed behaviour is pretty understandable.
 

MRLL

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Thanks for the reply.

Is there are code that can be used to read all 32 lines of 8-bit data?
 

FvM

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Is there are code that can be used to read all 32 lines of 8-bit data?
Obviously. Read one line, write the value to a memory location, repeat for each address.
 

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