VHDL implementation AES-128 decryption

[nihi]

Hello


I am doing my thesis project as VHDL Implementation of AES-128 algorithm. I have done the encryption and decryption using loop unrolled architecture but it is giving me high resource utilization. So, I am trying it by using State Machine. I have taken 4 states as RESET1, RESET2,IDLE, Processing. By using this I have got the encryption result but having problem in decryption.
I am attaching my code here.

View attachment aesdecryption.rar


Please help me doing this asap.

 

[TrickyDicky]

Do you have a testbench that can input test vectors and generate the correct results?
Have those should make debugging simple

 

[nihi]

Hello
Thanks for your reply. I am simulating it in ISE 9.2 so, I am just generating Test Bench Waveform. I am getting results for encryption so, I think there is some problem in code. please help me in finding the error.

 

[TrickyDicky]

Finding the error is YOUR job. if you have a specific problem, then come back with a question.

 

[nihi]

Hi
I got the error . Error is in Galois Field Multiplication part for mix column step, but I am not getting how to do it.

 

[ads-ee]

Hi
I got the error . Error is in Galois Field Multiplication part for mix column step, but I am not getting how to do it.

Then post a specific question about what you don't get about it, and the relevant code. I'm not willing to download a .rar file (probably others aren't as well) just to figure out where you have the Galois Field Multiplication code.

 

[nihi]

Hello

I solved the mix column step problem and the particular block is working fine, but still not getting the correct output of top module and I am not able to attach the single top level .vhd file so, making a zip file of that single vhd file and attaching it. please check it and help me.

 

[TrickyDicky]

What exactly do you want us to look at? What do you want comments on?
Where is the testbench code so you can debug it yourself in a simulator?

 

[nihi]

In OPERATION_COUNTER

 

[ads-ee]

I am not able to attach the single top level .vhd file so, making a zip file of that single vhd file and attaching it. please check it and help me.

I don't use rar and I don't want to download something to unrar a rar file, you claim it's a zip file WRONG.

Post the code directly in the thread using code tags. See this tutorial on code tags.

In OPERATION_COUNTER
View attachment 115682

And what are we supposed to determine by looking at an out of context code snippet?

Though I have determined that you don't know VHDL very well...
1. You should be using rising_edge(SYS_CLK) instead of SYS_CLK'event and SYS_CLK='1'
2. You don't know what should be placed in the sensitivity list of a process, why is PR_STATE in the sensitivity list of this process!?.

 

[mrflibble]

Psst, it's a rar. But never mind that, it's only one file so see below.

aesdercy.vhd:

---

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity AES_128_DECRYPT is
    Port (  SYS_CLK,RST : in STD_LOGIC;
                DECRY_IN : in  STD_LOGIC_VECTOR (127 downto 0);
                KEY_IN : in  STD_LOGIC_VECTOR (127 downto 0);
                START : in  STD_LOGIC;
                KEY_LOAD : in  STD_LOGIC;
                NEAR_DONE : out  STD_LOGIC;
                DONE : out  STD_LOGIC;
                BUSY : out  STD_LOGIC;
                DECRY_OUT : out  STD_LOGIC_VECTOR (127 downto 0));
end AES_128_DECRYPT;
 
architecture Behavioral of AES_128_DECRYPT is
 
----Sub Components Definitions
COMPONENT Key_Schedule_128
    PORT(
        SYS_CLK : IN std_logic;
        RST : IN std_logic;
        KEY_128 : IN std_logic_vector(127 downto 0);
        LOAD_KEY : IN std_logic;
        EXP_KEY : IN std_logic;          
        PAR_KEY : OUT std_logic_vector(127 downto 0)
        );
    END COMPONENT;
 
COMPONENT InvSubBytes
Port ( invSubBytes_IN : in  STD_LOGIC_VECTOR (127 downto 0);
           invSubBytes_OUT : out  STD_LOGIC_VECTOR (127 downto 0);
           SYS_CLK,RST : in  STD_LOGIC);
END COMPONENT;
 
COMPONENT InvShiftRows
    PORT(InvShiftRows_In : in  STD_LOGIC_VECTOR (127 downto 0);
           InvShiftRows_Out : out  STD_LOGIC_VECTOR (127 downto 0);
           Sys_Clk,RST : in  STD_LOGIC);
    END COMPONENT;
 
COMPONENT InvMixColumns
    PORT(
        SYS_CLK : IN std_logic;
        RST : IN std_logic;
        DATA_IN : IN std_logic_vector(127 downto 0);          
        DATA_OUT : OUT std_logic_vector(127 downto 0)
        );
    END COMPONENT;
 
COMPONENT AddRoundKey
    PORT(
        Data_IN : IN std_logic_vector(127 downto 0);
        Key_IN : IN std_logic_vector(127 downto 0);
        SYS_CLK : IN std_logic;
        RST : IN std_logic;          
        Data_OUT : OUT std_logic_vector(127 downto 0)
        );
    END COMPONENT;
----End Sub Components Definitions
 
type state is (RESET_1,RESET_2,IDLE,PROCESSING);  
signal pr_state,nx_state : state ;
 
SIGNAL RST_BUF : STD_LOGIC := '0';
SIGNAL BUSY_BUF : STD_LOGIC := '0';
SIGNAL DECRY_IN_BUFFER : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
 
SIGNAL OPN_COUNT : STD_LOGIC_VECTOR(1 downto 0) := "00";
SIGNAL RND_COUNT : STD_LOGIC_VECTOR(3 downto 0) := "0000";
SIGNAL RND_MUX_CNTRL  : STD_LOGIC_VECTOR(1 downto 0) := "00";
 
SIGNAL KEY_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvSubBytes_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvSubBytes_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvShiftRows_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvShiftRows_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvMixColumns_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvMixColumns_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL AddRoundKey_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL AddRoundKey_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
 
begin
 
--Instantiate Sub-Components
INST_Key_Schedule_128: Key_Schedule_128 PORT MAP(
        SYS_CLK => SYS_CLK,
        RST => RST_BUF,
        KEY_128 => KEY_IN,
        PAR_KEY => KEY_BUF,
        LOAD_KEY => KEY_LOAD,
        EXP_KEY => BUSY_BUF
    );
    
INST_InvShiftRows: InvShiftRows PORT MAP(
        invShiftRows_In => InvShiftRows_IN_BUF,
        invShiftRows_Out => InvShiftRows_OUT_BUF,
        Sys_Clk => SYS_CLK,
        RST => RST_BUF
    );  
 
INST_invSubBytes: invSubBytes PORT MAP(
        invSubBytes_IN => InvSubBytes_IN_BUF,
        invSubBytes_OUT => InvSubBytes_OUT_BUF,
        SYS_CLK => SYS_CLK,
        RST => RST_BUF
    );
 
INST_AddRoundKey: AddRoundKey PORT MAP(
        Data_IN => AddRoundKey_IN_BUF,
        Key_IN => KEY_BUF,
        Data_OUT => AddRoundKey_OUT_BUF,
        SYS_CLK => SYS_CLK,
        RST => RST_BUF
    );
 
INST_InvMixColumns: InvMixColumns PORT MAP(
        SYS_CLK => SYS_CLK,
        RST => RST_BUF,
        DATA_IN => InvMixColumns_IN_BUF,
        DATA_OUT => InvMixColumns_OUT_BUF 
    );
 
-----END Component Instatiation
 
STATE_MACHINE_HEAD : PROCESS (SYS_CLK,RST) ----State Machine Master Control
begin
    IF (SYS_CLK'event and SYS_CLK='1') then
        IF (RST = '1') then
            pr_state <= RESET_1;
        ELSE
            pr_state <= nx_state;
        END IF;
    END IF;
END PROCESS;
 
STATE_MACHINE_BODY : PROCESS (SYS_CLK,RST,PR_STATE,START,KEY_LOAD,OPN_COUNT,RND_COUNT) ---State Machine State Definitions
begin
    CASE pr_state is
        
        WHEN RESET_1 =>  --Master Reset State
            RST_BUF <= '1';
            BUSY_BUF  <= '0';
            nx_state <= RESET_2;
 
        WHEN RESET_2 =>  --Extra Reset State to prevent reset glitching
            RST_BUF <= '1';
            BUSY_BUF  <= '0';
            nx_state <= IDLE;
 
        WHEN IDLE =>   --Waiting for Key Load or Data/Start assertion
            RST_BUF <= '0';
            BUSY_BUF  <= '0';
            IF (START = '1') then
                nx_state <= PROCESSING;
            ELSE
                nx_state <= IDLE;
            END IF; 
                
        WHEN PROCESSING =>   --Enable step/round counters
            RST_BUF <= '0';
            BUSY_BUF  <= '1';
            IF (OPN_COUNT = "10" AND  RND_COUNT = X"0") then
                nx_state <= IDLE;
            ELSE
                nx_state <= PROCESSING;
            END IF;
    END CASE;
END PROCESS;    
                
 
OPERATIONS_COUNTER : PROCESS (SYS_CLK,PR_STATE)  ----Counts through each step and each round of cipher sequence, affects data path mux and state machine
begin   
    IF (SYS_CLK'event and SYS_CLK='1') then
        IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2 OR PR_STATE = IDLE) then
            OPN_COUNT <= "10";   --Step Counter Starts on 2 to correspond to AddRoundKey step at very start of cipher
            RND_COUNT <= "1010";
        ELSE
            OPN_COUNT <= OPN_COUNT + 1;   ---Always increment when processing
            IF OPN_COUNT = "11" then     ---Decrement at the last step of a round
                RND_COUNT <= RND_COUNT - 1;
            END IF;
        END IF;
    END IF;
END PROCESS;
 
 
 
DECRYPT_TEXT_OUTPUT_REGISTER : PROCESS(SYS_CLK,PR_STATE)   --Output Latch for decrytext
begin
    IF (SYS_CLK'event and SYS_CLK='1') then
        IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2) then
            DECRY_OUT <= (OTHERS => '0');
        ELSIF (OPN_COUNT = "10" AND  RND_COUNT = X"0") then
            DECRY_OUT <= AddRoundKey_OUT_BUF;
        END IF;
    END IF;
END PROCESS;
 
DECRYPT_DONE_SIGNAL_LATCH : PROCESS(SYS_CLK) ----Single Pulse Signal when dercryPted data is complete and output data is valid
begin
    IF (SYS_CLK'event and SYS_CLK='1') then
        IF (OPN_COUNT = "10" AND RND_COUNT = X"0") then
            DONE <= '1';
        ELSE
            DONE <= '0';
        END IF;
    END IF;
END PROCESS;
 
 
NEARLY_DONE_SIGNAL_LATCH : PROCESS(SYS_CLK)   -----Single Pule Signal when decrypted data is one clock cycle from completion: possiible trigger for continous loading
begin
 
IF (SYS_CLK'event and SYS_CLK='1') then
        IF (OPN_COUNT = "01" AND  RND_COUNT = X"0") then
            NEAR_DONE <= '1';
        ELSE
            NEAR_DONE <= '0';
        END IF;
    END IF;
END PROCESS;
 
DATA_PATH_MUX_CONTROL : PROCESS(SYS_CLK,PR_STATE)    
begin
    IF (SYS_CLK'event and SYS_CLK='1') then
        IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2 OR PR_STATE = IDLE) then
            AddRoundKey_IN_BUF  <=  DECRY_IN_BUFFER;
            else
                        AddRoundKey_IN_BUF  <=  InvSubBytes_OUT_BUF;
 
    END IF;
    END IF;
END PROCESS;
 
counter : PROCESS(SYS_CLK)
 begin
    IF (SYS_CLK'event and SYS_CLK='1') then
        IF (OPN_COUNT = "00" AND  RND_COUNT = X"9") then
          InvShiftRows_IN_BUF   <= AddRoundkey_OUT_BUF;
             else
                       InvShiftRows_IN_BUF  <= InvMixcolumns_OUT_BUF;
    end if;
    end if;
END PROCESS;
             
Decry_INPUT_REGISTER : PROCESS(SYS_CLK)
begin
    IF (SYS_CLK'event and SYS_CLK='1') then
        IF (RST = '1') then
            DECRY_IN_BUFFER <= (OTHERS => '0');
        ELSIF (START = '1' AND PR_STATE = IDLE) then
            DECRY_IN_BUFFER <= DECRY_IN;
        END IF;
    END IF;
END PROCESS;    
            
-----Set Core to Look BUSY during reset without actually asserting BUSY_BUF
BUSY_OUTPUT_MUX : PROCESS (BUSY_BUF,pr_state)
begin
    IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2) then
        BUSY <= '1';
    ELSE    
        BUSY <= BUSY_BUF;
    END IF;
END PROCESS;
 
---Fixed Pipeline Connections
InvSubBytes_IN_BUF  <= InvShiftRows_OUT_BUF; 
InvMixColumns_IN_BUF <= AddRoundKey_OUT_BUF;
 
-----END Async Signals-------------------   
            
end Behavioral;

---

Oh what the hell, as attachment as well.

@nihi: The forum attachment upload thingy only supports specific filename extensions. It's a bit silly, but there you have it. In the future you can rename it to something it supports (and tell people the original filename if it's not obvious). You can scroll down in the "upload attachment" dialogue to see which filename extensions are supported.

 

[ads-ee]

Besides the usage of the Synopsis libraries (which are superseded by the official IEEE numeric_std package)
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

You have most of your process sensitivity lists with extra signals other than SYS_CLK. As the majority of your processes are describing rising edge triggered (clocked) processes the only signal in the sensitivity list should be SYS_CLK.

I would also suggest using a consistent coding style. Things like the consistent use of upper/lower case and indentation go a long way to making your code, at the very least, look more professional.

Unless you have a problem with compiling the code or the simulation is doing something funny for no apparent reason. Functional problems in code you wrote is best debugged by you on a simulator. If you don't understand why some code is simulating something and producing unexpected waveforms, then you can post both a screen capture of the waveform and the code, but don't expect forum members to debug your functionality, that's not likely to happen.