VHDL : how to make design with generic number of components

[makanaky]

I need to make a design which uses a generic number of (4 to 2) priority encoders according to the input size . The design will be on many stages . For example if the input is 16 bits, then i will use 4 priority encoders in the first stage followed by a priority encoder in the 2nd stage.
If the input was 64 bit, then first stage will have 16 priority encoders , 2nd stage will have 4 priority encoders and 3rd stage will have alast priority encoder. My question is how to make all this Generic ?

 

[barry]

I haven't thought this all out, but I think you might be able to use a generic with a generate block.