[VHDL] How to generalize this function for variable input length

[syntax=vhdl]
constant ASCII_a: integer := 97;
constant ASCII_z: integer := 122;
subtype lower_case_character is integer range ASCII_a to ASCII_z;
type word is array (0 to string_length - 1) of lower_case_character;

function next_word (str: word) return word is
variable ret: word;
begin
	ret := str;
	if str(3) < lower_case_character'high then
		ret(3) := str(3) + 1;
	elsif str(2) < lower_case_character'high then
		ret(3) := lower_case_character'low;
		ret(2) := str(2) + 1;
	elsif str(1) < lower_case_character'high then
		ret(3) := lower_case_character'low;
		ret(2) := lower_case_character'low;
		ret(1) := str(1) + 1;
	elsif str(0) < lower_case_character'high then
		ret(3) := lower_case_character'low;
		ret(2) := lower_case_character'low;
		ret(1) := lower_case_character'low;
		ret(0) := str(0) + 1;
	end if;
	return ret;
end function next_word;[/syntax]

for i in a to be loop
  ...do something
end loop

while do_a_loop loop
  ..do something until do_a_loop is false.
end loop