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[VHDL] How to generalize this function for variable input length

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Alexium

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Greetings!

Please take a look at my function:
Code:
[syntax=vhdl]
constant ASCII_a: integer := 97;
constant ASCII_z: integer := 122;
subtype lower_case_character is integer range ASCII_a to ASCII_z;
type word is array (0 to string_length - 1) of lower_case_character;

function next_word (str: word) return word is
variable ret: word;
begin
	ret := str;
	if str(3) < lower_case_character'high then
		ret(3) := str(3) + 1;
	elsif str(2) < lower_case_character'high then
		ret(3) := lower_case_character'low;
		ret(2) := str(2) + 1;
	elsif str(1) < lower_case_character'high then
		ret(3) := lower_case_character'low;
		ret(2) := lower_case_character'low;
		ret(1) := str(1) + 1;
	elsif str(0) < lower_case_character'high then
		ret(3) := lower_case_character'low;
		ret(2) := lower_case_character'low;
		ret(1) := lower_case_character'low;
		ret(0) := str(0) + 1;
	end if;
	return ret;
end function next_word;[/syntax]
This function is for word length of 4, obviously, but the length is actually a generic constant. Generate statement is not available for function body. How can I deal with this problem? Maybe, redesign the data types I'm using to achieve the desired behaviour?
Thanks in advance!
 

TrickyDicky

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You can use loops inside funtions.

Code:
for i in a to be loop
  ...do something
end loop

while do_a_loop loop
  ..do something until do_a_loop is false.
end loop
 

Alexium

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Using FOR loop was my intention originally, but I don't understand how to do it. I need to terminate the loop once a digit has been incremented. Of course, I can use an FSM, but I really want to do it asynchronously, in 1 clock cycle.

---------- Post added at 12:30 ---------- Previous post was at 12:15 ----------

I did it, thanks for the tip!
 
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