[VHDL] How to change signal logic

[BlackHelicopter]

I am now a believer! I'll be honest I don't know much verilog so thanks for the simulation. Thats pretty cool to see what happens when 'a' gets shifted, I didn't know what to expect. It did exactly what the op wanted though so ship it!

 

[permute]

You can also divide the signals into two sets, one clocked by the rising edge of the clock, the others by the falling edge. The output can be connected to a mux (with clk as the sel line), or can be connected to an xor if the logic is setup correctly.

The mux isn't desirable in the FPGA, as the clock line would have to be routed in both fabric routing and on the clock network routing. This might have a large skew. Both have logic after the FF, which is not desirable for high speed systems.

the control logic can all be on the rising edge, and can generate a pair of signals, (ar xor ap, ar xor af). In this case, "ar" would be the output of "a" on the rising edge, and "af" would be the output after the falling edge. "ap" would be the logic of the previous falling edge. This could then be fed to an xor gate to generate a 2x rate signal which is encoded as a sequence of changes.

 

[mrflibble]

That's also how I'd do it (given the gun to the head). A set of FFs clocked on posedge, other set on negedge, and then xor the outputs. On an fpga with local clock inversion you would only need one clock net.

As ads_ee pointed out, that does require some constraints on placement to make sure this thing meets timing. But by RLOCing the FFs (ie RLOC the register declarations in your module) this won't be too painful.

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... I've become rather cynical in the short time I've been using this forum as many of the posters aren't willing to try anything before posting. They just want the answers handed to them. ...

Heh, it's hard not to become cynical with the large number of help vampires that periodically pop up.

Hi friends, this is Achmed/Timmy/Lingling here! I am exceedingly lazy and lack creativity. Please do my homework for me! kthxbye! ^^

Bless their bloodsucking little hearts. the lazy bastards.

 

[mrflibble]

Mmmh, as a followup to ads_ee's verilog code ...

When you have a module where the relative placement of FFs and such is a crucial part of the functionality of the design, how do you guys deal with the constraints?

I have this sortof rule that if a constraint is "a part of the functionality" (can't think of a better way to phrase it) then I try and put the constraint in the module itself. If only because that way I have this constraint precisely within the scope where it matters, and it prevents getting unmanageable .ucf files.

Whether this is a good idea or not is another matter. But given the constraint that the (placement) constraint is part of the function, how do you handle that?

So something like this:

---

Code Verilog - [expand]
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(* RLOC="X0Y0" *) reg a_pos; // posedge clocked FF
(* RLOC="X1Y0" *) reg a_neg; // negedge clocked FF in the neighbouring slice
 
always @(posedge clk)
    a_pos <= stuff;
 
always @(negedge clk)
    a_neg <= other_stuff;
 
assign a = a_pos ^ a_neg;

---

 

[ads_ee]

You can also divide the signals into two sets, one clocked by the rising edge of the clock, the others by the falling edge. The output can be connected to a mux (with clk as the sel line), or can be connected to an xor if the logic is setup correctly.

The mux isn't desirable in the FPGA, as the clock line would have to be routed in both fabric routing and on the clock network routing. This might have a large skew. Both have logic after the FF, which is not desirable for high speed systems.

the control logic can all be on the rising edge, and can generate a pair of signals, (ar xor ap, ar xor af). In this case, "ar" would be the output of "a" on the rising edge, and "af" would be the output after the falling edge. "ap" would be the logic of the previous falling edge. This could then be fed to an xor gate to generate a 2x rate signal which is encoded as a sequence of changes.

I initially thought of trying either this or my ugly band-aid implementation. I figured the band-aid would require less thought (design) on my part so I went with it. It would be interesting if you could design this version and we can compare the resource utilization results. Ignoring timing as I'm not interested in trying to come up with a set of constraints (i.e. to LAZY ;-) ).

Here is the reported utilization results from Vivado 14.4. Considering how simple the circuit was I doubt it will be any different using ISE.

[FONT=Lucida Console]+-------------------------------------------------------------+----------+-------+-----------+-------+
|                          Site Type                          |   Used   | Loced | Available | Util% |
+-------------------------------------------------------------+----------+-------+-----------+-------+
| Slice                                                       |        2 |     0 |     50950 |  0.01 |
| LUT as Logic                                                |        3 |     0 |    203800 |  0.01 |
|   using O5 output only                                      |        0 |       |           |       |
|   using O6 output only                                      |        3 |       |           |       |
|   using O5 and O6                                           |        0 |       |           |       |
| LUT as Memory                                               |        0 |     0 |     64000 |  0.00 |
|   LUT as Distributed RAM                                    |        0 |     0 |           |       |
|   LUT as Shift Register                                     |        0 |     0 |           |       |
| LUT Flip Flop Pairs                                         |        4 |     0 |    203800 |  0.01 |
|   fully used LUT-FF pairs                                   |        1 |       |           |       |
|   LUT-FF pairs with unused LUT                              |        1 |       |           |       |
|   LUT-FF pairs with unused Flip Flop                        |        2 |       |           |       |
| Unique Control Sets                                         |        2 |       |           |       |
| Minimum number of registers lost to control set restriction | 14(Lost) |       |           |       |
+-------------------------------------------------------------+----------+-------+-----------+-------+
[/FONT]

See it ate up 2 slices worth of registers :'(

Oh yeah, this is in a kintex 7 part (6-input LUTs)

 

[mrflibble]

I just ran the thought experiment and the result is the same. Two slices. One slice with posedge, one with negedge clocking. And the amount of logic + FFs is more than enough to fit the problem. Two control sets, check. And probably 2x2 FFs. Maybe reduce it two 3 ffs, but that would require actual thought. But the synthesis results you get look about right for what I'd expect for resource utilization.

PS: thought experiment was for lut-6 architecture too, because that's what I most often use. But would fit in lut-4 as well, due to the limited number of required inputs. So for a spartan-3 same amount of utilization. Well, except for now suddenly needing 2 clock nets because there's no local clock inversion feature.

PPS: On the subject of kintex 7 ... are there any affordable dev boards for that yet? And by affordable I mean for someone on a hobby budget. Last time I checked it was $1k+ ... a bit too much for me.

 

[ads_ee]

PPS: On the subject of kintex 7 ... are there any affordable dev boards for that yet? And by affordable I mean for someone on a hobby budget. Last time I checked it was $1k+ ... a bit too much for me.

Still in the ~$2K range but this board looks so nice.
https://www.xilinx.com/products/boards-and-kits/DK-K7-EMBD-G.htm

and with a 325T you can do so much. Too bad I don't have $2K to toss that direction.

 

[BlackHelicopter]

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Heh, it's hard not to become cynical with the large number of help vampires that periodically pop up.

Hi friends, this is Achmed/Timmy/Lingling here! I am exceedingly lazy and lack creativity. Please do my homework for me! kthxbye! ^^

This made my day! Never knew there was a term for them.

 

[mrflibble]

Still in the ~$2K range but this board looks so nice.
https://www.xilinx.com/products/boards-and-kits/DK-K7-EMBD-G.htm

and with a 325T you can do so much. Too bad I don't have $2K to toss that direction.

Oucho! $2K ... man, I can buy entire mountains of test gear on ebay for that. Guess I'll have to wait a little longer before them thar family 7 gadgets become feasible. And yes, a 325T sure would be nice. I've got drool all over the datasheet. ;-) Suppose I'll have to make do with spartan-6 for a little while longer.

This made my day! Never knew there was a term for them.

And they just keep on coming, almost with clockwork precision. Who needs gps when you have these. Maybe I could do a little HVDO (Help Vampire Disciplined Oscillator) project or something. Simple wget/perl script to get the datestamps of the next lazy person post, and put that inside the PLL loop filter.

 

[spade7]

Thank you all very much! Everything runs really good with the insertion of the second clk!