spade7
Newbie level 5
Hello,
I am rather new on VHDL. I have done some code in the past but I have a problem concerning how to manipulate B and C signals (as shown below). Actually, it is a state machine and I am trying to change the logic of these signals (B & C) in half of the clock pulse. Could you please give me some hints how to do it? Thank you
![clocksignals.jpg clocksignals.jpg](https://www.edaboard.com/data/attachments/28/28319-436217b5da9172518b051f31b8a74c95.jpg)
I am rather new on VHDL. I have done some code in the past but I have a problem concerning how to manipulate B and C signals (as shown below). Actually, it is a state machine and I am trying to change the logic of these signals (B & C) in half of the clock pulse. Could you please give me some hints how to do it? Thank you
![clocksignals.jpg clocksignals.jpg](https://www.edaboard.com/data/attachments/28/28319-436217b5da9172518b051f31b8a74c95.jpg)