You can also divide the signals into two sets, one clocked by the rising edge of the clock, the others by the falling edge. The output can be connected to a mux (with clk as the sel line), or can be connected to an xor if the logic is setup correctly.
The mux isn't desirable in the FPGA, as the clock line would have to be routed in both fabric routing and on the clock network routing. This might have a large skew. Both have logic after the FF, which is not desirable for high speed systems.
the control logic can all be on the rising edge, and can generate a pair of signals, (ar xor ap, ar xor af). In this case, "ar" would be the output of "a" on the rising edge, and "af" would be the output after the falling edge. "ap" would be the logic of the previous falling edge. This could then be fed to an xor gate to generate a 2x rate signal which is encoded as a sequence of changes.