VHDL: Help me generate a 1hz clock cycle

[karansinghdx]

Can anyone provide me code to generate a 1hz frequency clock generator from vhdl with clock cycle of 100Mhz default. please.

 

[vipinlal]

entity digi_clk is
port (clk1 : in std_logic;
       clk : out std_logic
     );
end digi_clk;

architecture Behavioral of digi_clk is

signal count : integer :=1;
signal clk : std_logic :='0';


 --clk generation.For 100 MHz clock this generates 1 Hz clock.
process(clk1) 
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;

Taken from https://vhdlguru.blogspot.com/