library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity top is
port (
clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(7 downto 0); -- 7 = width - 1
segment : out std_logic_vector(6 downto 0);
--second_bcd : out std_logic_vector(6 downto 0)
dp : out std_logic;
an : out std_logic_vector(3 downto 0)
);
constant width : integer := 8;
constant log_width : integer := integer(ceil(log2(real(width)))); -- 3
end top;
architecture arch of top is
signal first : std_logic_vector(log_width - 1 downto 0);
signal second : std_logic_vector(log_width - 1 downto 0);
signal validity : std_logic_vector(1 downto 0);
begin
dual_priority_encoder : entity work.dual_priority_encoder
generic map(input_width => width, output_width => log_width)
port map(clk => clk, reset => reset, input => input,
first => first, second => second, validity => validity);
first_bcd_segment : entity work.bcd
port map(clk => clk, reset => reset, bcd => first, segment => segment);
-- second_bcd_segment: entity work.bcd
-- port map(clk => clk, reset => reset, bcd => second, segment => second_bcd);
dp <= '1';
an <= "1110";
end arch;