shaiko
Advanced Member level 5
I want to write a VHDL function that calculates the sum of all the words of "array_x".
The array is defined in a package as follows:
The function's prototype is defined in a package as follows:
The function body is:
please tell me what you think.
The array is defined in a package as follows:
Code:
type array_words is array ( 0 to array_width - 1 ) of std_logic_vector ( array_depth - 1 downto 0 ) ;
The function's prototype is defined in a package as follows:
Code:
function sum ( some_array : array_words ) is
The function body is:
Code:
function sum ( some_array : array_words )
variable output : std_logic_vector ( array_depth - 1 downto 0 ) := ( others => '0' ) ;
begin
for index in 0 to array_depth - 2
loop
output <= some_array ( index ) + some_array ( index + 1 ) ;
end loop ;
return output ;