VHDL function for summing an array

[shaiko]

I want to write a VHDL function that calculates the sum of all the words of "array_x".

The array is defined in a package as follows:

type array_words is array ( 0 to array_width - 1 ) of std_logic_vector ( array_depth - 1 downto 0 ) ;

The function's prototype is defined in a package as follows:

function sum ( some_array : array_words ) is

The function body is:

function sum ( some_array : array_words )
variable output : std_logic_vector ( array_depth - 1 downto 0 ) := ( others => '0' ) ;
begin 
   for index in 0 to array_depth - 2 
   loop
      output <= some_array ( index ) + some_array ( index + 1 ) ;
   end loop ;
return output ;

please tell me what you think.

 

[FvM]

Instead of asking Edaboard members, why don't you use your simulator or synthesis tool to check for syntax errors?

Apart from syntax errors, the summing loop is obviously wrong. What's the idea behind adding two array elements? I guess, you want to sum all array elements to the variable sum. Thus something like

sum := sum + some_array (index);

over all array elements will be needed, including suitable initialization.

It would be also straightforward to use an arithmetic data type if you are doing arithmetic.

In case you are intending synthesized hardware, I presume you know that the summing method can only work for registers but not for block RAM.

 

[shaiko]

What about this:

function sum ( some_array : type_array_data_word_1 ) return unsigned is
variable output : unsigned ( constant_configuration_depth_memory_1 - 1 downto 0 ) := ( others => '0' ) ;
begin 
   for index in 0 to constant_configuration_depth_memory_1 - 1 
   loop
      output := output + some_array ( index ) ;
   end loop ;
   return output ;
end function sum ;

 

[TrickyDicky]

What does your simulator say?

I assume this isnt for synthesisable code, as the timing performance would be poor, getting much worse for larger arrays.