library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity practica_7_ejercicio_3 is
Port ( a : in UNSIGNED (3 downto 0);
b : in UNSIGNED (3 downto 0);
suma : out UNSIGNED (4 downto 0));
end practica_7_ejercicio_3;
architecture Behavioral of practica_7_ejercicio_3 is
--signal signoA: STD_LOGIC;
--signal signoB: STD_LOGIC;
begin
suma <= ('0' & a) + ('0' & b);
testbench:
[CODE]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity practica_7_ejercicio_3_TB is
-- Port ( );
end practica_7_ejercicio_3_TB;
architecture Behavioral of practica_7_ejercicio_3_TB is
component practica_7_ejercicio_3 is
Port ( a : in UNSIGNED (3 downto 0);
b : in UNSIGNED (3 downto 0);
suma : out UNSIGNED (4 downto 0));
end component;
signal T_a : UNSIGNED (3 downto 0);
signal T_b : UNSIGNED (3 downto 0);
signal T_suma : UNSIGNED (4 downto 0);
begin
ETIQUETA: practica_7_ejercicio_3 PORT MAP (a => T_a,
b => T_b,
suma => T_suma);
process
begin
T_a <= "1110";
for I in 0 to 8 loop
T_b <= UNSIGNED(TO_UNSIGNED(I,2));
wait for 1 us;
end loop;
T_b <= "0111";
for I in 0 to 8 loop
T_a <= UNSIGNED(TO_UNSIGNED(I,2));
wait for 1 us;
end loop;
wait;
end process;
end Behavioral