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# VHDL failing to create post-implementation timing simulation

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#### drcipres

##### Newbie
Im trying to add 2 4 bits numbers together and store the result in a 5 bits number. I've read in other forums that the recommended value type for this sort of arythmetic operations is unsigned, so im using those. Here is the .vhd code and the test bench
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity practica_7_ejercicio_3 is
Port ( a : in UNSIGNED (3 downto 0);
b : in UNSIGNED (3 downto 0);
suma : out UNSIGNED (4 downto 0));
end practica_7_ejercicio_3;

architecture Behavioral of practica_7_ejercicio_3 is

--signal signoA: STD_LOGIC;
--signal signoB: STD_LOGIC;

begin

suma <= ('0' & a) + ('0' & b);

testbench:

[CODE]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity practica_7_ejercicio_3_TB is
--  Port ( );
end practica_7_ejercicio_3_TB;

architecture Behavioral of practica_7_ejercicio_3_TB is

component practica_7_ejercicio_3 is
Port ( a : in UNSIGNED (3 downto 0);
b : in UNSIGNED (3 downto 0);
suma : out UNSIGNED (4 downto 0));
end component;

signal T_a : UNSIGNED (3 downto 0);
signal T_b : UNSIGNED (3 downto 0);
signal T_suma : UNSIGNED (4 downto 0);

begin

ETIQUETA: practica_7_ejercicio_3 PORT MAP (a => T_a,
b => T_b,
suma => T_suma);

process
begin
T_a <= "1110";
for I in 0 to 8 loop
T_b <= UNSIGNED(TO_UNSIGNED(I,2));
wait for 1 us;
end loop;

T_b <= "0111";
for I in 0 to 8 loop
T_a <= UNSIGNED(TO_UNSIGNED(I,2));
wait for 1 us;
end loop;

wait;
end process;

end Behavioral

end Behavioral;[/CODE]

These are the warnings that I get:
Code:
Synthesis
[Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

Implementation
Place Design
[Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer

Route Design
[Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate

[Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.

but im positive that most of these are normal, since our professor has told us to only use the switches and the LEDs in the .xdc file, so everything else is commented except these two lines on top of everything else
Code:
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

And in terms of errors, all I get is that it 'simulate' step failed and that it detected an error while running the simulation. Any ideas as to what could be causing this?

#### barry

All you've shown is (expected) warnings. You're asking about errors; maybe you should show us the errors!

But I think one problem you have is this: T_a <= UNSIGNED(TO_UNSIGNED(I,2));

You're converting I to an UNSIGNED 2 bit value, then you're converting it to an UNSIGNED value again, then you're assigning your 4 bit value, T_a, a 2 bit value.

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