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VHDL errror for real, std_logic_vector for sine value in DDS

sangitacp93

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I am trying to generate sine value for DDS, but I have error during synthesis. I have included ''ieee.math_real.all''

Error: [Synth 8-2778] type error near sin ; expected type std_logic_vector ["C:/Users/Sangita.POKHREL/Switches_led/Switches_led.srcs/sources_1/new/top.v":50]

[Synth 8-1731] cannot convert type real to type std_logic_vector ["C:/Users/Sangita.POKHREL/Switches_led/Switches_led.srcs/sources_1/new/top.v":52]

The code snippet is as below:
-- generate sine value

function init_lut_sin return t_lut_sin is
variable return_lut : t_lut_sin:=(others=>(others=>'0'));
variable v_tstep : real :=0.0;
variable v_qsine_sgn : std_logic_vector(C_LUT_BIT-1 downto 0):=(others=>'0');
constant step : real := 1.00/real(C_LUT_DEPTH);
begin
for count in 0 to C_LUT_DEPTH-1 loop
v_qsine_sgn := std_logic_vector(sin(MATH_2_PI*v_tstep)); --(sin (2PI/2^n))
return_lut(count) := v_qsine_sgn;
v_tstep := v_tstep + step;
end loop;
return return_lut;
end function init_lut_sin;
 

FvM

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Real has no representation in std_logic_vector, it's not synthesizable. Instead you need to convert real values to integer with a reasonable scaling factor and then to signed.

- - - Updated - - -

E.g.:

Code VHDL - [expand]
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v_qsine_sgn := std_logic_vector(to_unsigned(integer(2.0**(C_LUT_BIT-1)*sin(MATH_2_PI*v_tstep)),C_LUT_BIT));

 

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TrickyDicky

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are you trying to convert to float or fixed values?
VHDL 2008 has the fixed_pkg and float_pkg that can convert real values to either.

eg:

Code VHDL - [expand]
1
2
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use ieee.fixed_pkg.all;
 
constant my_real_as_a_slv : std_logic_vector(15 downto 0) := to_slv( to_ufixed( 8.257, 7, -8) ); -- converts 8.257 to a 8.8 usigned fixed, then slv

 

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