Gerry_robotics
Member level 1
Hi Folks,
I ran this through a design checker and I keep getting this Error:
It says it occurs at line 48. This is inside my "HORIZONTAL SYNC FREQUENCY" BLock of my code.
My code is shown below. I've added a commented sowing line 48.
I can't seem to figure this out, I've tried to switch to using BINARY numbers instead of decimal numbers
but that didn't work.
Any help here would be appreciated.
Thanks.
-Gerry
I ran this through a design checker and I keep getting this Error:
ERROR "Either type mismatch or no visible function for this case"
It says it occurs at line 48. This is inside my "HORIZONTAL SYNC FREQUENCY" BLock of my code.
My code is shown below. I've added a commented sowing line 48.
Code:
--
-- VHDL Architecture LAB_02_lib.HORZ_DEC_nty.HORZ_DEC_arch
--
-- Created:
-- by - Gerry.UNKNOWN (VIDEO)
-- at - 14:27:12 03/ 1/2012
--
-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY HORZ_DEC_nty IS
PORT(
clk_25Mhz : IN std_logic;
Char_Addr_Lines : IN std_logic_vector(9 downto 0); -- This is essentially just our counter "IMPUT" Bus for this Decoder Block. (The Previous BLock simply controls it to reset at 800)
State_639 : OUT std_logic;
State_659 : OUT std_logic;
State_000 : OUT std_logic;
State_755 : OUT std_logic;
State_640 : OUT std_logic;
State_799 : OUT std_logic;
State_658 : OUT std_logic;
State_756 : OUT std_logic;
Horz_sync_freq : OUT std_logic);
END HORZ_DEC_nty ;
ARCHITECTURE HORZ_DEC_arch OF HORZ_DEC_nty IS
SIGNAL SIG_horz_freq : std_logic;
SIGNAL SIG_h_count : std_logic_vector(9 DOWNTO 0);
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7);
SIGNAL state: STATE_TYPE;
BEGIN
------------------------- Horizontal Sync Frequency -----------------------------------
------------------------------- GENERATOR ---------------------------------------------
PROCESS
BEGIN
IF clk_25Mhz'EVENT AND clk_25Mhz = '1' THEN
IF (SIG_h_count <= 755) AND (SIG_h_count => 659) THEN --<<<<<<<< THIS IS LINE 48
SIG_horz_freq <= '0';
ELSE
SIG_horz_freq <= '1';
END IF;
END IF;
END PROCESS;
---------------------------------------------------------------------------------------
------------------------------ STATE SIGNALS ------------------------------------------
---------------------------------------------------------------------------------------
PROCESS (clk_25Mhz)
BEGIN
IF clk_25Mhz'EVENT AND clk_25Mhz = '1' THEN
CASE state IS
WHEN S0 => -- s0 is STATE 639
IF (SIG_h_count = 639) THEN
state <= S1;
State_639 <= '1';
END IF;
WHEN S1 => -- s1 is STATE 659
IF (SIG_h_count = 659) THEN
state <= S2;
State_659 <= '1';
END IF;
WHEN S2 => -- s2 is STATE 000
IF (SIG_h_count = 000) THEN
state <= S3;
State_000 <= '1';
END IF;
WHEN S3 => -- s3 is STATE 755
IF (SIG_h_count = 755) THEN
state <= S4;
State_755 <= '1';
END IF;
WHEN S4 => -- s4 is STATE 640
IF (SIG_h_count = 640) THEN
state <= S5;
State_640 <= '1';
END IF;
WHEN S5 => -- s5 is STATE 799
IF (SIG_h_count = 799) THEN
state <= S6;
State_799 <= '1';
END IF;
WHEN S6 => -- s6 is STATE 658
IF (SIG_h_count = 658) THEN
state <= S7;
State_658 <= '1';
END IF;
WHEN S7 => -- s7 is STATE 756
IF (SIG_h_count = 756) THEN
state <= S0;
State_756 <= '1';
END IF;
END CASE;
END IF;
END PROCESS;
Horz_sync_freq <= SIG_horz_freq;
Char_Addr_Lines <= SIG_h_count;
END ARCHITECTURE HORZ_DEC_arch;
I can't seem to figure this out, I've tried to switch to using BINARY numbers instead of decimal numbers
but that didn't work.
Any help here would be appreciated.
Thanks.
-Gerry