Given the usage of the word "program" I assume you're thinking in terms of software and wrote your code accordingly. You are obviously generating clk_3 someplace else in a different if statement. Doing so doesn't work the same way as software, signals in VHDL aren't "global". Post the entire code not just a snippet.
You're also creating output clocks from registers that you seem to be using as clocks. In general for FPGAs this is a bad practice as architecturally they don't have predictable routing access to the clock buffers from the fabric.
Regards