VHDL Error (10028): Can't resolve multiple constant drivers

[Mavnus04]

Hi all,

I am creating a program to move an object around the screen through my DE2 board. I am currently trying to create a clock with enough delay so the object does not move too quickly. When I reset my clock, which is a signal, back to zero I get the error "Error (10028): Can't resolve multiple constant drivers for net "clk_half_sec[14]"" for the entire std_logic_vector.

resetting clk_3 is the line that causes me problems. As soon as I comment it out, the file will compile fine. This code segment is within a if(rising_edge(clk_2)), which is within a process statement.

if(clk_3 = X"F424") then
	l_side <= l_side+1;
	r_side <= r_side+1;
	clk_3 <= x"0000";
end if;

Declaration:
signal clk_3 : std_logic_vector (15 downto 0);

I have no idea why this error is happening. Any help would be great. Please let me know if you want to see more the program.

 

[ads-ee]

Given the usage of the word "program" I assume you're thinking in terms of software and wrote your code accordingly. You are obviously generating clk_3 someplace else in a different if statement. Doing so doesn't work the same way as software, signals in VHDL aren't "global". Post the entire code not just a snippet.

You're also creating output clocks from registers that you seem to be using as clocks. In general for FPGAs this is a bad practice as architecturally they don't have predictable routing access to the clock buffers from the fabric.

Regards

 

[TrickyDicky]

Multiple constant drivers occurs when you drive the same signal from two or more processes. An assingment outside of a process counts as a stand alone process.