VHDL is a hardware description language, it's helpful to imagine the 2 flip-flop circuit described/modelled by the VHDL program in post #1. You'll understand why it must behave as it does. If you don't like the behaviour, design a different circuit.
Generally speaking, we can't suggest a different circuit with knowing the exact problem. We e.g. don't know if the actions specified in both processes must be clock synchronous.
Sketch a hardware circuit or a timing diagram or specify the intended behaviour otherwise.