[vhdl] define vector slice in package

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eng.amr2009

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Hi guys,


I'm implementing a certain packet decoder. The incoming packet is sliced according to certain ranges defined in a standard.

I want to define the slice ranges in a package so that my code is readable and generic at the same time.

For example if I'm slicing the control_field then I want to write for example

Code: 
frame_length <= control_field(frame_length_range);

where frame_length_range is (7 downto 0)

How can I define such range in a package ?

I used this syntax

Code: 
type frame_length_range is range 7 downto 0;

But when I run syntax check I receive the following error:

Code: 
Missing full type definition for  frame_length_range
 

Type declaration looks alright.

When you say syntax check do you mean compilation?

I believe your intention is to have a slice of the control_field. Lets say if control_field is a vector [31:0] then you may want to assign only the lower byte to frame_length? i.e. frame_length <= control_field[7:0]

If that is the case then I guess you have the concept a bit muddled up.

Type frame_length_range will help you define variables or signals of that type and it can't be used to generate a size as far as I can tell.

Let me see if I can find an example to do this generic slicing.
 

I found the solution.

The range can be defined as follows :

Code: 
subtype frame_length_range is natural range 15 downto 13;

Then I can index the vector with frame_length_range normally
 

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