let me answer these idividually
valid_vect(user_select)<=in_valid; -- <= "Type error near user_select; current type std_logic; expecting type natural"
a std_logic is not an integer. hence the failure
valid_vect(to_integer(unsigned(user_select)))<=in_valid; -- "Cannot convert type std_logic to type unsigned"
exactly like it says. a std_logic is not a vector, and so cannot be directly converted to an unsigned. Hence the failure.
valid_vect(to_integer(unsigned(""&user_select)))<=in_valid; -- <= does't work either : "found '4' definitions of operator "&", cannot determine excat overloaded mathich definitiion for "&" "
valid_vect(to_integer(unsigned("0"&user_select)))<=in_valid; -- <= does't work: "found '4' definitions of operator "&", cannot determine excat overloaded mathich definitiion for "&" "
These 2 are the same error. The problem is that doing this:
"0" & user_select
"" & user_select
is ambiguous because there are several types that are arrays of std_logic. So the compile doesnt know whether you want a std_logic_vector, a signed or an unsigned (I cant think of the 4th one). So to fix it, you need to tell the compiler which one you mean with a qualification (the ' character)
so this should work:
valid_vect(to_integer(unsigned( std_logic_vector'(""&user_select) )))< =in_valid;
BUT
because unsigned is also an array of std_logic, you might aswell skip the std_logic_vector step and qualify it as an unsigned:
valid_vect(to_integer( unsigned'( "" & user_select) ))< =in_valid;
This is a great lesson in the symmantics of VHDL, and the strong typing system (that some people loath). But with proper coding you can avoid most of the type conversions/qualifications.
---------- Post added at 10:57 ---------- Previous post was at 10:55 ----------
The lesson here would be to have user_select as an integer rather than std_logic.