arnoldwbush
Newbie level 4
Hi everyone
Consider the JK flip flop schematic below:
I write the following VHDL code for it:
When I synthesize it using Xilinx ISE 14.5, a combinatorial feedback loop is detected and the outputs q and qb remain uninitialized. However, when I implement the D Flip Flop in a similar manner, according the following schematic:
The D Flip Flop synthesizes and simulates just fine.
My question is, why does the JK Flip Flop not compile while the D Flip Flop does even though the code and schematic is so much similar?
Thanks
Arnold
Consider the JK flip flop schematic below:
I write the following VHDL code for it:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkff is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
signal a, b, c, d : std_logic;
begin
q <= d;
qb <= c;
a <= not (j and clk and c);
b <= not (k and clk and d);
d <= not (c and a);
c <= not (d and b);
end Behavioral;
When I synthesize it using Xilinx ISE 14.5, a combinatorial feedback loop is detected and the outputs q and qb remain uninitialized. However, when I implement the D Flip Flop in a similar manner, according the following schematic:
Code:
entity dff is
Port ( d : in STD_LOGIC;
c : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
signal e, f, g, h, i, j, k, l, qs, qbs : std_logic;
begin
qs <= k nand qbs;
qbs <= l nand qs;
e <= not c;
h <= not e;
f <= not(d and e);
g <= not(e and f);
i <= not(f and j);
j <= not(g and i);
k <= not(i and h);
l <= not(h and k);
q <= qs;
qb <= qbs;
end Behavioral;
The D Flip Flop synthesizes and simulates just fine.
My question is, why does the JK Flip Flop not compile while the D Flip Flop does even though the code and schematic is so much similar?
Thanks
Arnold