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VHDL coding style problem!!!!

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dimon_k

Newbie level 2
Hi all,

I have written this lines

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library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

a<= '1' when wr_addr > 6 + rd_addr else '0';

I want a to be 1 when difference between wr_addr and rd_addr is more then 6 e.g I have 6 written addresses in fifo,

but in the lab I see that it doesn't work properly.

writing :

f

Code VHDL - [expand]1
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a<= '1' when fifo_lvl > 6  else '0';

solves the problem...

Can anybody explane what is the problem here???

thanks

Last edited by a moderator:

Consider that 6 + rd_addr can overflow the unsigned(3 downto 0) range. Then both constructs behave different.

So you say that if rd_addr = 14 then rd_addr + 6 will be 4 because it is unsigned

So you say that if rd_addr = 14 then rd_addr + 6 will be 4 because it is unsigned
Not exactly. The integer expression rd_addr +6 has the value 20. An unsigned[3 downto 0] fifo_lvl is assigned a value of 4.

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