dimon_k
Newbie level 2
Hi all,
I have written this lines
I want a to be 1 when difference between wr_addr and rd_addr is more then 6 e.g I have 6 written addresses in fifo,
but in the lab I see that it doesn't work properly.
writing :
f
solves the problem...
Can anybody explane what is the problem here???
thanks
I have written this lines
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; signal wr_addr :std_logic_vector(3 downto 0); -- fifo write address signal rd_addr :std_logic_vector(3 downto 0); -- fifo read address a<= '1' when wr_addr > 6 + rd_addr else '0';
I want a to be 1 when difference between wr_addr and rd_addr is more then 6 e.g I have 6 written addresses in fifo,
but in the lab I see that it doesn't work properly.
writing :
f
Code VHDL - [expand] 1 2 ifo_lvl<= wr_addr - rd_addr ; a<= '1' when fifo_lvl > 6 else '0';
solves the problem...
Can anybody explane what is the problem here???
thanks
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