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VHDL code weird type error

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NeginMadani

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I would really appreciate your help. I wrote the following testbench code to test my 6th order FIR filter. It worked perfectly for my behavioral code, but when I try to use it after synthesis for my structural gate-level netlist, I get this error:

ERROR:HDLCompiler:1728 - "/home/..." Line 24: Type error near xin ; current type signed; expected type signed
ERROR:HDLCompiler:1728 - "/home/..." Line 25: Type error near yout ; current type signed; expected type signed
ERROR:HDLCompiler:854 - "/home/..." Line 12: Unit <behavior> ignored due to previous errors.
VHDL file /home/... ignored due to errors


Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY test_six_order_fir_filter IS
END test_six_order_fir_filter;
 
ARCHITECTURE behavior OF test_six_order_fir_filter IS 
 
   signal clk : std_logic := '0';
   signal xin : signed(7 downto 0) := (others => '0');
   signal yout : signed(15 downto 0) := (others => '0');
   constant clk_period : time := 10 ns;
 
BEGIN
 
    -- instantiate the Unit Under Test (UUT)
   uut: entity work.six_order_fir_filter PORT MAP (
          clk => clk,
          xin => xin,  -- Line 24
          yout => yout -- Line 25
        );
 
   -- clock process definitions
   clk_process :process
   begin
        Clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
    
   -- stimulus process, using various values as inputs to observe the output. The input value changes after 1 clock period = 10ns.
   stim_proc: process
   begin        
      wait for clk_period*2;
        xin <= to_signed(-4,8); 
          wait for 1*clk_period;
        xin <= to_signed(2,8); 
          wait for 1*clk_period;
        xin <= to_signed(0,8); 
          wait for 1*clk_period;
        xin <= to_signed(-2,8); 
          wait for 1*clk_period;
        xin <= to_signed(5,8); 
          wait for 1*clk_period;
        xin <= to_signed(4,8); 
          wait for 1*clk_period;
        xin <= to_signed(-5,8); 
          wait for 1*clk_period;
        xin <= to_signed(6,8); 
          wait for 1*clk_period;
          xin <= to_signed(10,8); 
          wait for 1*clk_period;
        xin <= to_signed(0,8);
      wait;
end process;

 

please post the code for the six_order_fir_filter block. This error usually occurs when one file uses numeric_std, and the other uses std_logic_arith.
 
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The testbench worked fine for my behavioral code, but I get the error when I try to use it for my structural gate-level netlist:

Code:
------------------------
--header file
------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity inv is
port(inb: in STD_logic;
     outb: out STD_Logic);
end inv;
architecture structure of inv is
begin
outb <= not (inb);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity nand2 is
port(a, b: in STD_logic;
	outb: out STD_Logic);
end nand2;
architecture structure of nand2 is
begin
outb <= not(a and b);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity nand3 is
port(a, b, c: in STD_logic;
           outb: out STD_Logic);
end nand3 ;
architecture structure of nand3 is
begin
outb <= not(a and b and c);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity nand4 is
port(a, b, c, d: in STD_logic;
	      outb: out STD_Logic);
end nand4 ;
architecture structure of nand4 is
begin
outb <= not(a and b and c and d);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity nor2 is
port(a, b: in STD_logic;
	outb: out STD_Logic);
end nor2 ;
architecture structure of nor2 is
begin
outb <= not(a or b);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity nor3 is
port(a, b, c: in STD_logic;
	   outb: out STD_Logic);
end nor3 ;
architecture structure of nor3 is
begin
outb <= not(a or b or c);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity xor2 is
port(a, b: in STD_logic;
        outb: out STD_Logic);
end xor2 ;
architecture structure of xor2 is
begin
outb <= (a xor b);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity aoi12 is
port(a, b, c: in STD_logic;
	   outb: out STD_Logic);
end aoi12 ;
architecture structure of aoi12 is
begin
outb <= not(a or (b and c));
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity aoi22 is
port(a, b, c, d: in STD_logic;
              outb: out STD_Logic);
end aoi22 ;
architecture structure of aoi22 is
begin
outb <= not((a and b) or (c and d));
end structure;


library IEEE;
use IEEE.std_logic_1164.all;

entity oai12 is
port(a, b, c: in STD_logic;
	   outb: out STD_Logic);
end oai12;
architecture structure of oai12 is
begin
outb <= not(a and (b or c));
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity oai22 is
port(a, b, c, d: in STD_logic;
              outb: out STD_Logic);
end oai22; 
architecture structure of oai22 is
begin
outb <= not((a or b) and (c or d));
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity dff is
port(d, gclk, rnot: in STD_logic;
q: out STD_Logic);
end dff;
architecture structure of dff is
begin
start: process(gclk,rnot)
begin
if ( rising_edge(gclk)) then
	if (rnot = '0') then
	q <= '0';
	elsif (rnot = '1') then
	q <= d;
	end if;
end if;

end process;
end structure;

--------------------------
-- gate-level netlist
--------------------------

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_six_order_fir_filter is

-- define attributes
attribute ENUM_ENCODING : STRING;

-- define any necessary types
type SIGNED is array (INTEGER range <>) of std_logic;

end CONV_PACK_six_order_fir_filter;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_six_order_fir_filter.all;

entity six_order_fir_filter is

   port( clk : in std_logic;  xin : in SIGNED (7 downto 0);  yout : out SIGNED 
         (15 downto 0));

end six_order_fir_filter;

architecture SYN_Behavioral of six_order_fir_filter is

   component inv
      port( inb : in std_logic;  outb : out std_logic);
   end component;
   
   component nor2
      port( a, b : in std_logic;  outb : out std_logic);
   end component;
   
   component nand2
      port( a, b : in std_logic;  outb : out std_logic);
   end component;
   
   component aoi22
      port( a, b, c, d : in std_logic;  outb : out std_logic);
   end component;
   
   component xor2
      port( a, b : in std_logic;  outb : out std_logic);
   end component;
   
   component oai22
      port( a, b, c, d : in std_logic;  outb : out std_logic);
   end component;
   
   component aoi12
      port( b, c, a : in std_logic;  outb : out std_logic);
   end component;
   
   component oai12
      port( b, c, a : in std_logic;  outb : out std_logic);
   end component;
   
   component nor3
      port( a, b, c : in std_logic;  outb : out std_logic);
   end component;
   
   component nand3
      port( a, b, c : in std_logic;  outb : out std_logic);
   end component;
   
   component nand4
      port( a, b, c, d : in std_logic;  outb : out std_logic);
   end component;
   
   component dff
      port( d, gclk, rnot : in std_logic;  q : out std_logic);
   end component;
   
   signal q1_15_port, q1_14_port, q1_13_port, q1_12_port, q1_11_port, 
      q1_10_port, q1_9_port, q1_8_port, q1_7_port, q1_6_port, q1_5_port, 
      q1_4_port, q1_3_port, add1_15_port, add1_14_port, add1_13_port, 
      add1_12_port, add1_11_port, add1_10_port, add1_9_port, add1_8_port, 
      add1_7_port, add1_6_port, add1_5_port, add1_4_port, add1_3_port, 
      add1_2_port, add1_1_port, q2_15_port, q2_14_port, q2_13_port, q2_12_port,
      q2_11_port, q2_10_port, q2_9_port, q2_8_port, q2_7_port, q2_6_port, 
      q2_5_port, q2_4_port, q2_3_port, q2_2_port, q2_1_port, add2_15_port, 
      add2_14_port, add2_13_port, add2_12_port, add2_11_port, add2_10_port, 
      add2_9_port, add2_8_port, add2_7_port, add2_6_port, add2_5_port, 
      add2_4_port, add2_3_port, add2_2_port, add2_1_port, q3_15_port, 
      q3_14_port, q3_13_port, q3_12_port, q3_11_port, q3_10_port, q3_9_port, 
      q3_8_port, q3_7_port, q3_6_port, q3_5_port, q3_4_port, q3_3_port, 
      q3_2_port, q3_1_port, add3_15_port, add3_14_port, add3_13_port, 
      add3_12_port, add3_11_port, add3_10_port, add3_9_port, add3_8_port, 
      add3_7_port, add3_6_port, add3_5_port, add3_4_port, add3_3_port, 
      add3_2_port, add3_1_port, q4_15_port, q4_14_port, q4_13_port, q4_12_port,
      q4_11_port, q4_10_port, q4_9_port, q4_8_port, q4_7_port, q4_6_port, 
      q4_5_port, q4_4_port, q4_3_port, q4_2_port, q4_1_port, add4_15_port, 
      add4_14_port, add4_13_port, add4_12_port, add4_11_port, add4_10_port, 
      add4_9_port, add4_8_port, add4_7_port, add4_6_port, add4_5_port, 
      add4_4_port, add4_3_port, add4_2_port, add4_1_port, q5_15_port, 
      q5_14_port, q5_13_port, q5_12_port, q5_11_port, q5_10_port, q5_9_port, 
      q5_8_port, q5_7_port, q5_6_port, q5_5_port, q5_4_port, q5_3_port, 
      add5_15_port, add5_14_port, add5_13_port, add5_12_port, add5_11_port, 
      add5_10_port, add5_9_port, add5_8_port, add5_7_port, add5_6_port, 
      add5_5_port, add5_4_port, add5_3_port, add5_2_port, add5_1_port, 
      q6_15_port, q6_14_port, q6_13_port, q6_12_port, q6_11_port, q6_10_port, 
      q6_9_port, q6_8_port, q6_7_port, q6_6_port, q6_5_port, q6_4_port, 
      q6_3_port, q6_2_port, q6_1_port, add6_15_port, add6_14_port, add6_13_port
      , add6_12_port, add6_11_port, add6_10_port, add6_9_port, add6_8_port, 
      add6_7_port, add6_6_port, add6_5_port, add6_4_port, add6_3_port, 
      add6_2_port, add6_1_port, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, 
      n13, n14, n15, n16, d_flipflop1_n16, d_flipflop1_n15, d_flipflop1_n14, 
      d_flipflop1_n13, d_flipflop1_n12, d_flipflop1_n11, d_flipflop1_n10, 
      d_flipflop1_n9, d_flipflop1_n8, d_flipflop1_n7, d_flipflop1_n6, 
      d_flipflop1_n5, d_flipflop1_n4, d_flipflop1_n3, d_flipflop1_n2, n27, n28,
      n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43
      , n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, 
      n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72
      , n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, 
      n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, 
      n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, 
      n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, 
      n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, 
      n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, 
      n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, 
      n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, 
      n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, 
      n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, 
      n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, 
      n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, 
      n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, 
      n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, 
      n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, 
      n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, 
      n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, 
      n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, 
      n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, 
      n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, 
      n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, 
      n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, 
      n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, 
      n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, 
      n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, 
      n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, 
      n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, 
      n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, 
      n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, 
      n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, 
      n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, 
      n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, 
      n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, 
      n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, 
      n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, 
      n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, 
      n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, 
      n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, 
      n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, 
      n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, 
      n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, 
      n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, 
      n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, 
      n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, 
      n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, 
      n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, 
      n629 : std_logic;

begin
   
   yout_reg_15_inst : dff port map( d => add6_15_port, gclk => clk, rnot => n16
                           , q => yout(15));
   yout_reg_14_inst : dff port map( d => add6_14_port, gclk => clk, rnot => n15
                           , q => yout(14));
   yout_reg_13_inst : dff port map( d => add6_13_port, gclk => clk, rnot => n14
                           , q => yout(13));
   yout_reg_12_inst : dff port map( d => add6_12_port, gclk => clk, rnot => n13
                           , q => yout(12));
   yout_reg_11_inst : dff port map( d => add6_11_port, gclk => clk, rnot => n12
                           , q => yout(11));
   yout_reg_10_inst : dff port map( d => add6_10_port, gclk => clk, rnot => n11
                           , q => yout(10));
   yout_reg_9_inst : dff port map( d => add6_9_port, gclk => clk, rnot => n10, 
                           q => yout(9));
   yout_reg_8_inst : dff port map( d => add6_8_port, gclk => clk, rnot => n9, q
                           => yout(8));
   yout_reg_7_inst : dff port map( d => add6_7_port, gclk => clk, rnot => n8, q
                           => yout(7));
   yout_reg_6_inst : dff port map( d => add6_6_port, gclk => clk, rnot => n7, q
                           => yout(6));
   yout_reg_5_inst : dff port map( d => add6_5_port, gclk => clk, rnot => n6, q
                           => yout(5));
   yout_reg_4_inst : dff port map( d => add6_4_port, gclk => clk, rnot => n5, q
                           => yout(4));
   yout_reg_3_inst : dff port map( d => add6_3_port, gclk => clk, rnot => n4, q
                           => yout(3));
   yout_reg_2_inst : dff port map( d => add6_2_port, gclk => clk, rnot => n3, q
                           => yout(2));
   yout_reg_1_inst : dff port map( d => add6_1_port, gclk => clk, rnot => n2, q
                           => yout(1));
   n2 <= '1';
   n3 <= '1';
   n4 <= '1';
   n5 <= '1';
   n6 <= '1';
   n7 <= '1';
   n8 <= '1';
   n9 <= '1';
   n10 <= '1';
   n11 <= '1';
   n12 <= '1';
   n13 <= '1';
   n14 <= '1';
   n15 <= '1';
   n16 <= '1';
   d_flipflop1_n16 <= '1';
   d_flipflop1_n15 <= '1';
   d_flipflop1_n14 <= '1';
   d_flipflop1_n13 <= '1';
   d_flipflop1_n12 <= '1';
   d_flipflop1_n11 <= '1';
   d_flipflop1_n10 <= '1';
   d_flipflop1_n9 <= '1';
   d_flipflop1_n8 <= '1';
   d_flipflop1_n7 <= '1';
   d_flipflop1_n6 <= '1';
   d_flipflop1_n5 <= '1';
   d_flipflop1_n4 <= '1';
   d_flipflop1_n3 <= '1';
   d_flipflop1_n2 <= '1';
   d_flipflop1_t_reg_1_inst : dff port map( d => xin(0), gclk => clk, rnot => 
                           d_flipflop1_n2, q => add1_1_port);
   d_flipflop1_t_reg_2_inst : dff port map( d => xin(1), gclk => clk, rnot => 
                           d_flipflop1_n3, q => add1_2_port);
   d_flipflop1_t_reg_3_inst : dff port map( d => xin(2), gclk => clk, rnot => 
                           d_flipflop1_n4, q => q1_3_port);
   d_flipflop1_t_reg_4_inst : dff port map( d => xin(3), gclk => clk, rnot => 
                           d_flipflop1_n5, q => q1_4_port);
   d_flipflop1_t_reg_5_inst : dff port map( d => xin(4), gclk => clk, rnot => 
                           d_flipflop1_n6, q => q1_5_port);
   d_flipflop1_t_reg_6_inst : dff port map( d => xin(5), gclk => clk, rnot => 
                           d_flipflop1_n7, q => q1_6_port);
   d_flipflop1_t_reg_7_inst : dff port map( d => xin(6), gclk => clk, rnot => 
                           d_flipflop1_n8, q => q1_7_port);
   d_flipflop1_t_reg_8_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n9, q => q1_8_port);
   d_flipflop1_t_reg_9_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n10, q => q1_9_port);
   d_flipflop1_t_reg_10_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n11, q => q1_10_port);
   d_flipflop1_t_reg_11_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n12, q => q1_11_port);
   d_flipflop1_t_reg_12_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n13, q => q1_12_port);
   d_flipflop1_t_reg_13_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n14, q => q1_13_port);
   d_flipflop1_t_reg_14_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n15, q => q1_14_port);
   d_flipflop1_t_reg_15_inst : dff port map( d => xin(7), gclk => clk, rnot => 
                           d_flipflop1_n16, q => q1_15_port);
   n629 <= '1';
   n628 <= '1';
   n627 <= '1';
   n626 <= '1';
   n625 <= '1';
   n624 <= '1';
   n623 <= '1';
   n622 <= '1';
   n621 <= '1';
   n620 <= '1';
   n619 <= '1';
   n618 <= '1';
   n617 <= '1';
   n616 <= '1';
   n615 <= '1';
   d_flipflop6_t_reg_1_inst : dff port map( d => add5_1_port, gclk => clk, rnot
                           => n615, q => q6_1_port);
   d_flipflop6_t_reg_2_inst : dff port map( d => add5_2_port, gclk => clk, rnot
                           => n616, q => q6_2_port);
   d_flipflop6_t_reg_3_inst : dff port map( d => add5_3_port, gclk => clk, rnot
                           => n617, q => q6_3_port);
   d_flipflop6_t_reg_4_inst : dff port map( d => add5_4_port, gclk => clk, rnot
                           => n618, q => q6_4_port);
   d_flipflop6_t_reg_5_inst : dff port map( d => add5_5_port, gclk => clk, rnot
                           => n619, q => q6_5_port);
   d_flipflop6_t_reg_6_inst : dff port map( d => add5_6_port, gclk => clk, rnot
                           => n620, q => q6_6_port);
   d_flipflop6_t_reg_7_inst : dff port map( d => add5_7_port, gclk => clk, rnot
                           => n621, q => q6_7_port);
   d_flipflop6_t_reg_8_inst : dff port map( d => add5_8_port, gclk => clk, rnot
                           => n622, q => q6_8_port);
   d_flipflop6_t_reg_9_inst : dff port map( d => add5_9_port, gclk => clk, rnot
                           => n623, q => q6_9_port);
   d_flipflop6_t_reg_10_inst : dff port map( d => add5_10_port, gclk => clk, 
                           rnot => n624, q => q6_10_port);
   d_flipflop6_t_reg_11_inst : dff port map( d => add5_11_port, gclk => clk, 
                           rnot => n625, q => q6_11_port);
   d_flipflop6_t_reg_12_inst : dff port map( d => add5_12_port, gclk => clk, 
                           rnot => n626, q => q6_12_port);
   d_flipflop6_t_reg_13_inst : dff port map( d => add5_13_port, gclk => clk, 
                           rnot => n627, q => q6_13_port);
   d_flipflop6_t_reg_14_inst : dff port map( d => add5_14_port, gclk => clk, 
                           rnot => n628, q => q6_14_port);
   d_flipflop6_t_reg_15_inst : dff port map( d => add5_15_port, gclk => clk, 
                           rnot => n629, q => q6_15_port);
   n614 <= '1';
   n613 <= '1';
   n612 <= '1';
   n611 <= '1';
   n610 <= '1';
   n609 <= '1';
   n608 <= '1';
   n607 <= '1';
   n606 <= '1';
   n605 <= '1';
   n604 <= '1';
   n603 <= '1';
   n602 <= '1';
   n601 <= '1';
   n600 <= '1';
   d_flipflop5_t_reg_1_inst : dff port map( d => add4_1_port, gclk => clk, rnot
                           => n600, q => add5_1_port);
   d_flipflop5_t_reg_2_inst : dff port map( d => add4_2_port, gclk => clk, rnot
                           => n601, q => add5_2_port);
   d_flipflop5_t_reg_3_inst : dff port map( d => add4_3_port, gclk => clk, rnot
                           => n602, q => q5_3_port);
   d_flipflop5_t_reg_4_inst : dff port map( d => add4_4_port, gclk => clk, rnot
                           => n603, q => q5_4_port);
   d_flipflop5_t_reg_5_inst : dff port map( d => add4_5_port, gclk => clk, rnot
                           => n604, q => q5_5_port);
   d_flipflop5_t_reg_6_inst : dff port map( d => add4_6_port, gclk => clk, rnot
                           => n605, q => q5_6_port);
   d_flipflop5_t_reg_7_inst : dff port map( d => add4_7_port, gclk => clk, rnot
                           => n606, q => q5_7_port);
   d_flipflop5_t_reg_8_inst : dff port map( d => add4_8_port, gclk => clk, rnot
                           => n607, q => q5_8_port);
   d_flipflop5_t_reg_9_inst : dff port map( d => add4_9_port, gclk => clk, rnot
                           => n608, q => q5_9_port);
   d_flipflop5_t_reg_10_inst : dff port map( d => add4_10_port, gclk => clk, 
                           rnot => n609, q => q5_10_port);
   d_flipflop5_t_reg_11_inst : dff port map( d => add4_11_port, gclk => clk, 
                           rnot => n610, q => q5_11_port);
   d_flipflop5_t_reg_12_inst : dff port map( d => add4_12_port, gclk => clk, 
                           rnot => n611, q => q5_12_port);
   d_flipflop5_t_reg_13_inst : dff port map( d => add4_13_port, gclk => clk, 
                           rnot => n612, q => q5_13_port);
   d_flipflop5_t_reg_14_inst : dff port map( d => add4_14_port, gclk => clk, 
                           rnot => n613, q => q5_14_port);
   d_flipflop5_t_reg_15_inst : dff port map( d => add4_15_port, gclk => clk, 
                           rnot => n614, q => q5_15_port);
   n599 <= '1';
   n598 <= '1';
   n597 <= '1';
   n596 <= '1';
   n595 <= '1';
   n594 <= '1';
   n593 <= '1';
   n592 <= '1';
   n591 <= '1';
   n590 <= '1';
   n589 <= '1';
   n588 <= '1';
   n587 <= '1';
   n586 <= '1';
   n585 <= '1';
   d_flipflop4_t_reg_1_inst : dff port map( d => add3_1_port, gclk => clk, rnot
                           => n585, q => q4_1_port);
   d_flipflop4_t_reg_2_inst : dff port map( d => add3_2_port, gclk => clk, rnot
                           => n586, q => q4_2_port);
   d_flipflop4_t_reg_3_inst : dff port map( d => add3_3_port, gclk => clk, rnot
                           => n587, q => q4_3_port);
   d_flipflop4_t_reg_4_inst : dff port map( d => add3_4_port, gclk => clk, rnot
                           => n588, q => q4_4_port);
   d_flipflop4_t_reg_5_inst : dff port map( d => add3_5_port, gclk => clk, rnot
                           => n589, q => q4_5_port);
   d_flipflop4_t_reg_6_inst : dff port map( d => add3_6_port, gclk => clk, rnot
                           => n590, q => q4_6_port);
   d_flipflop4_t_reg_7_inst : dff port map( d => add3_7_port, gclk => clk, rnot
                           => n591, q => q4_7_port);
   d_flipflop4_t_reg_8_inst : dff port map( d => add3_8_port, gclk => clk, rnot
                           => n592, q => q4_8_port);
   d_flipflop4_t_reg_9_inst : dff port map( d => add3_9_port, gclk => clk, rnot
                           => n593, q => q4_9_port);
   d_flipflop4_t_reg_10_inst : dff port map( d => add3_10_port, gclk => clk, 
                           rnot => n594, q => q4_10_port);
   d_flipflop4_t_reg_11_inst : dff port map( d => add3_11_port, gclk => clk, 
                           rnot => n595, q => q4_11_port);
   d_flipflop4_t_reg_12_inst : dff port map( d => add3_12_port, gclk => clk, 
                           rnot => n596, q => q4_12_port);
   d_flipflop4_t_reg_13_inst : dff port map( d => add3_13_port, gclk => clk, 
                           rnot => n597, q => q4_13_port);
   d_flipflop4_t_reg_14_inst : dff port map( d => add3_14_port, gclk => clk, 
                           rnot => n598, q => q4_14_port);
   d_flipflop4_t_reg_15_inst : dff port map( d => add3_15_port, gclk => clk, 
                           rnot => n599, q => q4_15_port);
   n584 <= '1';
   n583 <= '1';
   n582 <= '1';
   n581 <= '1';
   n580 <= '1';
   n579 <= '1';
   n578 <= '1';
   n577 <= '1';
   n576 <= '1';
   n575 <= '1';
   n574 <= '1';
   n573 <= '1';
   n572 <= '1';
   n571 <= '1';
   n570 <= '1';
   d_flipflop3_t_reg_1_inst : dff port map( d => add2_1_port, gclk => clk, rnot
                           => n570, q => q3_1_port);
   d_flipflop3_t_reg_2_inst : dff port map( d => add2_2_port, gclk => clk, rnot
                           => n571, q => q3_2_port);
   d_flipflop3_t_reg_3_inst : dff port map( d => add2_3_port, gclk => clk, rnot
                           => n572, q => q3_3_port);
   d_flipflop3_t_reg_4_inst : dff port map( d => add2_4_port, gclk => clk, rnot
                           => n573, q => q3_4_port);
   d_flipflop3_t_reg_5_inst : dff port map( d => add2_5_port, gclk => clk, rnot
                           => n574, q => q3_5_port);
   d_flipflop3_t_reg_6_inst : dff port map( d => add2_6_port, gclk => clk, rnot
                           => n575, q => q3_6_port);
   d_flipflop3_t_reg_7_inst : dff port map( d => add2_7_port, gclk => clk, rnot
                           => n576, q => q3_7_port);
   d_flipflop3_t_reg_8_inst : dff port map( d => add2_8_port, gclk => clk, rnot
                           => n577, q => q3_8_port);
   d_flipflop3_t_reg_9_inst : dff port map( d => add2_9_port, gclk => clk, rnot
                           => n578, q => q3_9_port);
   d_flipflop3_t_reg_10_inst : dff port map( d => add2_10_port, gclk => clk, 
                           rnot => n579, q => q3_10_port);
   d_flipflop3_t_reg_11_inst : dff port map( d => add2_11_port, gclk => clk, 
                           rnot => n580, q => q3_11_port);
   d_flipflop3_t_reg_12_inst : dff port map( d => add2_12_port, gclk => clk, 
                           rnot => n581, q => q3_12_port);
   d_flipflop3_t_reg_13_inst : dff port map( d => add2_13_port, gclk => clk, 
                           rnot => n582, q => q3_13_port);
   d_flipflop3_t_reg_14_inst : dff port map( d => add2_14_port, gclk => clk, 
                           rnot => n583, q => q3_14_port);
   d_flipflop3_t_reg_15_inst : dff port map( d => add2_15_port, gclk => clk, 
                           rnot => n584, q => q3_15_port);
   n569 <= '1';
   n568 <= '1';
   n567 <= '1';
   n566 <= '1';
   n565 <= '1';
   n564 <= '1';
   n563 <= '1';
   n562 <= '1';
   n561 <= '1';
   n560 <= '1';
   n559 <= '1';
   n558 <= '1';
   n557 <= '1';
   n556 <= '1';
   n555 <= '1';
   d_flipflop2_t_reg_1_inst : dff port map( d => add1_1_port, gclk => clk, rnot
                           => n555, q => q2_1_port);
   d_flipflop2_t_reg_2_inst : dff port map( d => add1_2_port, gclk => clk, rnot
                           => n556, q => q2_2_port);
   d_flipflop2_t_reg_3_inst : dff port map( d => add1_3_port, gclk => clk, rnot
                           => n557, q => q2_3_port);
   d_flipflop2_t_reg_4_inst : dff port map( d => add1_4_port, gclk => clk, rnot
                           => n558, q => q2_4_port);
   d_flipflop2_t_reg_5_inst : dff port map( d => add1_5_port, gclk => clk, rnot
                           => n559, q => q2_5_port);
   d_flipflop2_t_reg_6_inst : dff port map( d => add1_6_port, gclk => clk, rnot
                           => n560, q => q2_6_port);
   d_flipflop2_t_reg_7_inst : dff port map( d => add1_7_port, gclk => clk, rnot
                           => n561, q => q2_7_port);
   d_flipflop2_t_reg_8_inst : dff port map( d => add1_8_port, gclk => clk, rnot
                           => n562, q => q2_8_port);
   d_flipflop2_t_reg_9_inst : dff port map( d => add1_9_port, gclk => clk, rnot
                           => n563, q => q2_9_port);
   d_flipflop2_t_reg_10_inst : dff port map( d => add1_10_port, gclk => clk, 
                           rnot => n564, q => q2_10_port);
   d_flipflop2_t_reg_11_inst : dff port map( d => add1_11_port, gclk => clk, 
                           rnot => n565, q => q2_11_port);
   d_flipflop2_t_reg_12_inst : dff port map( d => add1_12_port, gclk => clk, 
                           rnot => n566, q => q2_12_port);
   d_flipflop2_t_reg_13_inst : dff port map( d => add1_13_port, gclk => clk, 
                           rnot => n567, q => q2_13_port);
   d_flipflop2_t_reg_14_inst : dff port map( d => add1_14_port, gclk => clk, 
                           rnot => n568, q => q2_14_port);
   d_flipflop2_t_reg_15_inst : dff port map( d => add1_15_port, gclk => clk, 
                           rnot => n569, q => q2_15_port);
   yout(0) <= '0';
   U30 : xor2 port map( a => n27, b => n28, outb => add6_9_port);
   U31 : xor2 port map( a => n29, b => n30, outb => n28);
   U32 : xor2 port map( a => n31, b => n32, outb => add6_8_port);
   U33 : xor2 port map( a => q6_8_port, b => xin(7), outb => n32);
   U34 : xor2 port map( a => n33, b => n34, outb => add6_7_port);
   U35 : xor2 port map( a => q6_7_port, b => xin(6), outb => n34);
   U36 : xor2 port map( a => n35, b => n36, outb => add6_6_port);
   U37 : xor2 port map( a => q6_6_port, b => xin(5), outb => n36);
   U38 : xor2 port map( a => n37, b => n38, outb => add6_5_port);
   U39 : xor2 port map( a => q6_5_port, b => xin(4), outb => n38);
   U40 : xor2 port map( a => n39, b => n40, outb => add6_4_port);
   U41 : xor2 port map( a => q6_4_port, b => xin(3), outb => n40);
   U42 : xor2 port map( a => n41, b => n42, outb => add6_3_port);
   U43 : xor2 port map( a => q6_3_port, b => xin(2), outb => n42);
   U44 : xor2 port map( a => n43, b => n44, outb => add6_2_port);
   U45 : xor2 port map( a => q6_2_port, b => n45, outb => n44);
   U46 : xor2 port map( a => q6_1_port, b => xin(0), outb => add6_1_port);
   U47 : xor2 port map( a => n46, b => n47, outb => add6_15_port);
   U48 : xor2 port map( a => q6_15_port, b => xin(7), outb => n47);
   U49 : aoi22 port map( a => n48, b => n49, c => n50, d => n30, outb => n46);
   U50 : nand2 port map( a => xin(7), b => n51, outb => n48);
   U51 : xor2 port map( a => n51, b => n52, outb => add6_14_port);
   U52 : xor2 port map( a => n49, b => n30, outb => n52);
   U53 : inv port map( inb => q6_14_port, outb => n49);
   U54 : inv port map( inb => n50, outb => n51);
   U55 : aoi22 port map( a => n53, b => xin(7), c => n54, d => q6_13_port, outb
                           => n50);
   U56 : nand2 port map( a => n30, b => n55, outb => n54);
   U57 : xor2 port map( a => n53, b => n56, outb => add6_13_port);
   U58 : xor2 port map( a => q6_13_port, b => xin(7), outb => n56);
   U59 : inv port map( inb => n55, outb => n53);
   U60 : aoi22 port map( a => n57, b => xin(7), c => n58, d => q6_12_port, outb
                           => n55);
   U61 : nand2 port map( a => n30, b => n59, outb => n58);
   U62 : xor2 port map( a => n57, b => n60, outb => add6_12_port);
   U63 : xor2 port map( a => q6_12_port, b => xin(7), outb => n60);
   U64 : inv port map( inb => n59, outb => n57);
   U65 : aoi22 port map( a => n61, b => xin(7), c => n62, d => q6_11_port, outb
                           => n59);
   U66 : nand2 port map( a => n30, b => n63, outb => n62);
   U67 : xor2 port map( a => n61, b => n64, outb => add6_11_port);
   U68 : xor2 port map( a => q6_11_port, b => xin(7), outb => n64);
   U69 : inv port map( inb => n63, outb => n61);
   U70 : aoi22 port map( a => n65, b => xin(7), c => n66, d => q6_10_port, outb
                           => n63);
   U71 : inv port map( inb => n67, outb => n66);
   U72 : nor2 port map( a => xin(7), b => n65, outb => n67);
   U73 : xor2 port map( a => n65, b => n68, outb => add6_10_port);
   U74 : xor2 port map( a => q6_10_port, b => xin(7), outb => n68);
   U75 : oai22 port map( a => n30, b => n69, c => n70, d => n29, outb => n65);
   U76 : inv port map( inb => q6_9_port, outb => n29);
   U77 : nor2 port map( a => n27, b => xin(7), outb => n70);
   U78 : inv port map( inb => n69, outb => n27);
   U79 : oai22 port map( a => xin(7), b => n31, c => q6_8_port, d => n71, outb 
                           => n69);
   U80 : nor2 port map( a => n30, b => n72, outb => n71);
   U81 : inv port map( inb => n72, outb => n31);
   U82 : oai22 port map( a => xin(6), b => n33, c => q6_7_port, d => n73, outb 
                           => n72);
   U83 : nor2 port map( a => n74, b => n75, outb => n73);
   U84 : inv port map( inb => n74, outb => n33);
   U85 : oai22 port map( a => xin(5), b => n35, c => q6_6_port, d => n76, outb 
                           => n74);
   U86 : nor2 port map( a => n77, b => n78, outb => n76);
   U87 : inv port map( inb => n77, outb => n35);
   U88 : oai22 port map( a => xin(4), b => n37, c => q6_5_port, d => n79, outb 
                           => n77);
   U89 : nor2 port map( a => n80, b => n81, outb => n79);
   U90 : inv port map( inb => n80, outb => n37);
   U91 : oai22 port map( a => xin(3), b => n39, c => q6_4_port, d => n82, outb 
                           => n80);
   U92 : nor2 port map( a => n83, b => n84, outb => n82);
   U93 : inv port map( inb => n83, outb => n39);
   U94 : oai22 port map( a => xin(2), b => n41, c => q6_3_port, d => n85, outb 
                           => n83);
   U95 : nor2 port map( a => n86, b => n87, outb => n85);
   U96 : inv port map( inb => n86, outb => n41);
   U97 : oai22 port map( a => xin(1), b => n88, c => q6_2_port, d => n89, outb 
                           => n86);
   U98 : nor2 port map( a => n43, b => n45, outb => n89);
   U99 : inv port map( inb => n43, outb => n88);
   U100 : nand2 port map( a => q6_1_port, b => xin(0), outb => n43);
   U101 : xor2 port map( a => n90, b => n91, outb => add5_9_port);
   U102 : xor2 port map( a => q5_9_port, b => xin(6), outb => n91);
   U103 : xor2 port map( a => n92, b => n93, outb => add5_8_port);
   U104 : xor2 port map( a => q5_8_port, b => xin(5), outb => n93);
   U105 : xor2 port map( a => n94, b => n95, outb => add5_7_port);
   U106 : xor2 port map( a => q5_7_port, b => xin(4), outb => n95);
   U107 : xor2 port map( a => n96, b => n97, outb => add5_6_port);
   U108 : xor2 port map( a => q5_6_port, b => xin(3), outb => n97);
   U109 : xor2 port map( a => n98, b => n99, outb => add5_5_port);
   U110 : xor2 port map( a => q5_5_port, b => xin(2), outb => n99);
   U111 : xor2 port map( a => n100, b => n101, outb => add5_4_port);
   U112 : xor2 port map( a => q5_4_port, b => n45, outb => n101);
   U113 : inv port map( inb => n102, outb => add5_3_port);
   U114 : aoi12 port map( b => n103, c => q5_3_port, a => n104, outb => n102);
   U115 : xor2 port map( a => n105, b => n106, outb => add5_15_port);
   U116 : xor2 port map( a => q5_15_port, b => xin(7), outb => n106);
   U117 : oai22 port map( a => n30, b => n107, c => q5_14_port, d => n108, outb
                           => n105);
   U118 : nor2 port map( a => n109, b => xin(7), outb => n108);
   U119 : inv port map( inb => n109, outb => n107);
   U120 : xor2 port map( a => n109, b => n110, outb => add5_14_port);
   U121 : xor2 port map( a => q5_14_port, b => xin(7), outb => n110);
   U122 : aoi22 port map( a => n30, b => n111, c => n112, d => q5_13_port, outb
                           => n109);
   U123 : nand2 port map( a => n113, b => xin(7), outb => n112);
   U124 : inv port map( inb => n113, outb => n111);
   U125 : xor2 port map( a => n113, b => n114, outb => add5_13_port);
   U126 : xor2 port map( a => q5_13_port, b => xin(7), outb => n114);
   U127 : oai22 port map( a => n30, b => n115, c => q5_12_port, d => n116, outb
                           => n113);
   U128 : nor2 port map( a => n117, b => xin(7), outb => n116);
   U129 : inv port map( inb => n117, outb => n115);
   U130 : xor2 port map( a => n117, b => n118, outb => add5_12_port);
   U131 : xor2 port map( a => q5_12_port, b => xin(7), outb => n118);
   U132 : aoi22 port map( a => n30, b => n119, c => n120, d => q5_11_port, outb
                           => n117);
   U133 : nand2 port map( a => n121, b => xin(7), outb => n120);
   U134 : inv port map( inb => n121, outb => n119);
   U135 : xor2 port map( a => n121, b => n122, outb => add5_11_port);
   U136 : xor2 port map( a => q5_11_port, b => xin(7), outb => n122);
   U137 : oai22 port map( a => n30, b => n123, c => q5_10_port, d => n124, outb
                           => n121);
   U138 : nor2 port map( a => n125, b => xin(7), outb => n124);
   U139 : inv port map( inb => n125, outb => n123);
   U140 : xor2 port map( a => n125, b => n126, outb => add5_10_port);
   U141 : xor2 port map( a => q5_10_port, b => xin(7), outb => n126);
   U142 : aoi22 port map( a => n75, b => n127, c => n128, d => q5_9_port, outb 
                           => n125);
   U143 : nand2 port map( a => xin(6), b => n90, outb => n128);
   U144 : inv port map( inb => n90, outb => n127);
   U145 : aoi22 port map( a => n78, b => n129, c => n130, d => q5_8_port, outb 
                           => n90);
   U146 : nand2 port map( a => xin(5), b => n92, outb => n130);
   U147 : inv port map( inb => n92, outb => n129);
   U148 : aoi22 port map( a => n81, b => n131, c => n132, d => q5_7_port, outb 
                           => n92);
   U149 : nand2 port map( a => xin(4), b => n94, outb => n132);
   U150 : inv port map( inb => n94, outb => n131);
   U151 : aoi22 port map( a => n84, b => n133, c => n134, d => q5_6_port, outb 
                           => n94);
   U152 : nand2 port map( a => xin(3), b => n96, outb => n134);
   U153 : inv port map( inb => n96, outb => n133);
   U154 : aoi22 port map( a => n87, b => n135, c => n136, d => q5_5_port, outb 
                           => n96);
   U155 : nand2 port map( a => xin(2), b => n98, outb => n136);
   U156 : inv port map( inb => n98, outb => n135);
   U157 : aoi22 port map( a => n45, b => n100, c => n137, d => q5_4_port, outb 
                           => n98);
   U158 : nand2 port map( a => xin(1), b => n104, outb => n137);
   U159 : inv port map( inb => n104, outb => n100);
   U160 : nor2 port map( a => n103, b => q5_3_port, outb => n104);
   U161 : xor2 port map( a => n138, b => n139, outb => add4_9_port);
   U162 : xor2 port map( a => q4_9_port, b => n140, outb => n138);
   U163 : xor2 port map( a => n141, b => n142, outb => add4_8_port);
   U164 : xor2 port map( a => q4_8_port, b => n143, outb => n141);
   U165 : xor2 port map( a => n144, b => n145, outb => add4_7_port);
   U166 : xor2 port map( a => q4_7_port, b => n146, outb => n145);
   U167 : xor2 port map( a => n147, b => n148, outb => add4_6_port);
   U168 : xor2 port map( a => q4_6_port, b => n149, outb => n148);
   U169 : xor2 port map( a => n150, b => n151, outb => add4_5_port);
   U170 : xor2 port map( a => q4_5_port, b => n152, outb => n151);
   U171 : xor2 port map( a => n153, b => n154, outb => add4_4_port);
   U172 : xor2 port map( a => q4_4_port, b => n155, outb => n154);
   U173 : xor2 port map( a => n156, b => n157, outb => add4_3_port);
   U174 : xor2 port map( a => q4_3_port, b => xin(2), outb => n157);
   U175 : xor2 port map( a => n158, b => n159, outb => add4_2_port);
   U176 : xor2 port map( a => q4_2_port, b => n45, outb => n159);
   U177 : xor2 port map( a => q4_1_port, b => xin(0), outb => add4_1_port);
   U178 : xor2 port map( a => n160, b => n161, outb => add4_15_port);
   U179 : xor2 port map( a => q4_15_port, b => n162, outb => n161);
   U180 : aoi22 port map( a => n163, b => n164, c => n165, d => n166, outb => 
                           n160);
   U181 : nand2 port map( a => n167, b => n162, outb => n163);
   U182 : xor2 port map( a => n167, b => n168, outb => add4_14_port);
   U183 : xor2 port map( a => n164, b => n166, outb => n168);
   U184 : inv port map( inb => q4_14_port, outb => n164);
   U185 : inv port map( inb => n165, outb => n167);
   U186 : aoi22 port map( a => n162, b => n169, c => n170, d => q4_13_port, 
                           outb => n165);
   U187 : nand2 port map( a => n171, b => n166, outb => n170);
   U188 : xor2 port map( a => n169, b => n172, outb => add4_13_port);
   U189 : xor2 port map( a => q4_13_port, b => n162, outb => n172);
   U190 : inv port map( inb => n171, outb => n169);
   U191 : oai22 port map( a => n162, b => n173, c => q4_12_port, d => n174, 
                           outb => n171);
   U192 : nor2 port map( a => n166, b => n175, outb => n174);
   U193 : xor2 port map( a => n173, b => n176, outb => add4_12_port);
   U194 : xor2 port map( a => q4_12_port, b => n162, outb => n176);
   U195 : inv port map( inb => n175, outb => n173);
   U196 : oai22 port map( a => n177, b => n178, c => q4_11_port, d => n179, 
                           outb => n175);
   U197 : nor2 port map( a => n180, b => n181, outb => n179);
   U198 : xor2 port map( a => n178, b => n182, outb => add4_11_port);
   U199 : xor2 port map( a => q4_11_port, b => n177, outb => n182);
   U200 : inv port map( inb => n181, outb => n177);
   U201 : oai22 port map( a => n183, b => n184, c => q4_10_port, d => n185, 
                           outb => n181);
   U202 : nor2 port map( a => n186, b => n187, outb => n185);
   U203 : xor2 port map( a => n184, b => n188, outb => add4_10_port);
   U204 : xor2 port map( a => q4_10_port, b => n183, outb => n188);
   U205 : inv port map( inb => n187, outb => n183);
   U206 : oai22 port map( a => n189, b => n190, c => q4_9_port, d => n191, outb
                           => n187);
   U207 : nor2 port map( a => n139, b => n140, outb => n191);
   U208 : inv port map( inb => n140, outb => n189);
   U209 : oai22 port map( a => n192, b => n193, c => q4_8_port, d => n194, outb
                           => n140);
   U210 : nor2 port map( a => n142, b => n143, outb => n194);
   U211 : inv port map( inb => n143, outb => n192);
   U212 : oai22 port map( a => n146, b => n144, c => q4_7_port, d => n195, outb
                           => n143);
   U213 : nor2 port map( a => n196, b => n197, outb => n195);
   U214 : inv port map( inb => n196, outb => n144);
   U215 : oai22 port map( a => n149, b => n147, c => q4_6_port, d => n198, outb
                           => n196);
   U216 : nor2 port map( a => n199, b => n200, outb => n198);
   U217 : inv port map( inb => n200, outb => n149);
   U218 : oai22 port map( a => n152, b => n150, c => q4_5_port, d => n201, outb
                           => n200);
   U219 : nor2 port map( a => n202, b => n203, outb => n201);
   U220 : inv port map( inb => n203, outb => n152);
   U221 : oai22 port map( a => n155, b => n153, c => q4_4_port, d => n204, outb
                           => n203);
   U222 : nor2 port map( a => n205, b => n206, outb => n204);
   U223 : inv port map( inb => n206, outb => n155);
   U224 : oai22 port map( a => xin(2), b => n156, c => q4_3_port, d => n207, 
                           outb => n206);
   U225 : nor2 port map( a => n87, b => n208, outb => n207);
   U226 : inv port map( inb => n208, outb => n156);
   U227 : oai22 port map( a => xin(1), b => n209, c => q4_2_port, d => n210, 
                           outb => n208);
   U228 : nor2 port map( a => n45, b => n158, outb => n210);
   U229 : inv port map( inb => n158, outb => n209);
   U230 : nand2 port map( a => q4_1_port, b => xin(0), outb => n158);
   U231 : xor2 port map( a => n211, b => n212, outb => add3_9_port);
   U232 : xor2 port map( a => q3_9_port, b => n213, outb => n211);
   U233 : xor2 port map( a => n214, b => n215, outb => add3_8_port);
   U234 : xor2 port map( a => q3_8_port, b => n216, outb => n215);
   U235 : xor2 port map( a => n217, b => n218, outb => add3_7_port);
   U236 : xor2 port map( a => q3_7_port, b => n219, outb => n218);
   U237 : xor2 port map( a => n220, b => n221, outb => add3_6_port);
   U238 : xor2 port map( a => q3_6_port, b => n222, outb => n221);
   U239 : xor2 port map( a => n223, b => n224, outb => add3_5_port);
   U240 : xor2 port map( a => q3_5_port, b => n225, outb => n224);
   U241 : xor2 port map( a => n226, b => n227, outb => add3_4_port);
   U242 : xor2 port map( a => q3_4_port, b => n228, outb => n227);
   U243 : xor2 port map( a => n229, b => n230, outb => add3_3_port);
   U244 : xor2 port map( a => q3_3_port, b => n231, outb => n230);
   U245 : xor2 port map( a => n232, b => n233, outb => add3_2_port);
   U246 : xor2 port map( a => q3_2_port, b => n234, outb => n233);
   U247 : xor2 port map( a => q3_1_port, b => xin(0), outb => add3_1_port);
   U248 : xor2 port map( a => n235, b => n236, outb => add3_15_port);
   U249 : xor2 port map( a => n237, b => q3_15_port, outb => n235);
   U250 : oai22 port map( a => n238, b => n239, c => n240, d => n241, outb => 
                           n237);
   U251 : inv port map( inb => q3_14_port, outb => n241);
   U252 : nor2 port map( a => n242, b => n236, outb => n240);
   U253 : inv port map( inb => n236, outb => n238);
   U254 : xor2 port map( a => n236, b => n243, outb => add3_14_port);
   U255 : xor2 port map( a => q3_14_port, b => n242, outb => n243);
   U256 : inv port map( inb => n239, outb => n242);
   U257 : oai22 port map( a => n244, b => n245, c => q3_13_port, d => n246, 
                           outb => n239);
   U258 : inv port map( inb => n247, outb => n246);
   U259 : nand2 port map( a => n245, b => n244, outb => n247);
   U260 : nor2 port map( a => n248, b => n30, outb => n236);
   U261 : oai12 port map( b => n249, c => n250, a => n251, outb => n248);
   U262 : nand4 port map( a => n252, b => n253, c => n254, d => n255, outb => 
                           n251);
   U263 : aoi12 port map( b => n256, c => n254, a => n257, outb => n250);
   U264 : oai12 port map( b => n258, c => n259, a => n260, outb => n256);
   U265 : inv port map( inb => n261, outb => n259);
   U266 : xor2 port map( a => n245, b => n262, outb => add3_13_port);
   U267 : xor2 port map( a => q3_13_port, b => n244, outb => n262);
   U268 : aoi22 port map( a => n263, b => n264, c => n265, d => n266, outb => 
                           n244);
   U269 : inv port map( inb => n267, outb => n266);
   U270 : nor2 port map( a => n264, b => n263, outb => n267);
   U271 : inv port map( inb => q3_12_port, outb => n265);
   U272 : inv port map( inb => n268, outb => n245);
   U273 : xor2 port map( a => n269, b => n270, outb => n268);
   U274 : nand2 port map( a => n271, b => n249, outb => n270);
   U275 : inv port map( inb => n253, outb => n249);
   U276 : aoi12 port map( b => n254, c => n272, a => n257, outb => n269);
   U277 : xor2 port map( a => n273, b => n264, outb => add3_12_port);
   U278 : xor2 port map( a => n274, b => n272, outb => n264);
   U279 : oai12 port map( b => n258, c => n275, a => n260, outb => n272);
   U280 : nand2 port map( a => n254, b => n276, outb => n274);
   U281 : inv port map( inb => n257, outb => n276);
   U282 : nor2 port map( a => n277, b => n278, outb => n257);
   U283 : nand2 port map( a => n278, b => n277, outb => n254);
   U284 : oai12 port map( b => n279, c => n280, a => n271, outb => n277);
   U285 : nand3 port map( a => n280, b => n281, c => n279, outb => n271);
   U286 : aoi22 port map( a => xin(7), b => n282, c => n283, d => n284, outb =>
                           n279);
   U287 : nand2 port map( a => n285, b => n286, outb => n278);
   U288 : xor2 port map( a => q3_12_port, b => n263, outb => n273);
   U289 : oai22 port map( a => n287, b => n288, c => q3_11_port, d => n289, 
                           outb => n263);
   U290 : nor2 port map( a => n290, b => n291, outb => n289);
   U291 : inv port map( inb => n291, outb => n287);
   U292 : xor2 port map( a => n292, b => n290, outb => add3_11_port);
   U293 : inv port map( inb => n288, outb => n290);
   U294 : xor2 port map( a => n275, b => n293, outb => n288);
   U295 : nand2 port map( a => n255, b => n260, outb => n293);
   U296 : nand2 port map( a => n294, b => n295, outb => n260);
   U297 : inv port map( inb => n258, outb => n255);
   U298 : nor2 port map( a => n295, b => n294, outb => n258);
   U299 : nor2 port map( a => n296, b => n297, outb => n294);
   U300 : xor2 port map( a => n286, b => n285, outb => n295);
   U301 : nor2 port map( a => n298, b => n299, outb => n285);
   U302 : xor2 port map( a => n281, b => n280, outb => n286);
   U303 : aoi12 port map( b => n300, c => n301, a => n81, outb => n280);
   U304 : inv port map( inb => n302, outb => n301);
   U305 : nor2 port map( a => n252, b => n261, outb => n275);
   U306 : nor2 port map( a => n303, b => n304, outb => n261);
   U307 : nor2 port map( a => n305, b => n304, outb => n252);
   U308 : inv port map( inb => n306, outb => n304);
   U309 : xor2 port map( a => q3_11_port, b => n291, outb => n292);
   U310 : oai22 port map( a => n307, b => n308, c => q3_10_port, d => n309, 
                           outb => n291);
   U311 : nor2 port map( a => n310, b => n311, outb => n309);
   U312 : inv port map( inb => n311, outb => n307);
   U313 : xor2 port map( a => n312, b => n310, outb => add3_10_port);
   U314 : inv port map( inb => n308, outb => n310);
   U315 : nand2 port map( a => n313, b => n314, outb => n308);
   U316 : inv port map( inb => n315, outb => n314);
   U317 : aoi12 port map( b => n303, c => n305, a => n306, outb => n315);
   U318 : nand3 port map( a => n305, b => n303, c => n306, outb => n313);
   U319 : xor2 port map( a => n297, b => n296, outb => n306);
   U320 : nand2 port map( a => n316, b => n317, outb => n296);
   U321 : xor2 port map( a => n318, b => n299, outb => n297);
   U322 : xor2 port map( a => n319, b => n302, outb => n299);
   U323 : oai12 port map( b => n320, c => n321, a => n322, outb => n302);
   U324 : nand2 port map( a => xin(4), b => n300, outb => n319);
   U325 : inv port map( inb => n298, outb => n318);
   U326 : oai12 port map( b => n323, c => n324, a => xin(3), outb => n298);
   U327 : nand3 port map( a => n325, b => n326, c => n327, outb => n303);
   U328 : oai12 port map( b => n328, c => n329, a => n330, outb => n305);
   U329 : xor2 port map( a => q3_10_port, b => n311, outb => n312);
   U330 : oai22 port map( a => n331, b => n332, c => q3_9_port, d => n333, outb
                           => n311);
   U331 : nor2 port map( a => n212, b => n213, outb => n333);
   U332 : inv port map( inb => n212, outb => n332);
   U333 : xor2 port map( a => n334, b => n330, outb => n212);
   U334 : inv port map( inb => n335, outb => n330);
   U335 : xor2 port map( a => n326, b => n336, outb => n335);
   U336 : nand2 port map( a => n325, b => n327, outb => n336);
   U337 : xor2 port map( a => n316, b => n317, outb => n326);
   U338 : xor2 port map( a => n324, b => n337, outb => n317);
   U339 : nor2 port map( a => n323, b => n84, outb => n337);
   U340 : nor2 port map( a => n338, b => n339, outb => n323);
   U341 : inv port map( inb => n340, outb => n324);
   U342 : oai22 port map( a => n341, b => n300, c => n342, d => n343, outb => 
                           n340);
   U343 : nor2 port map( a => n344, b => n341, outb => n342);
   U344 : inv port map( inb => n345, outb => n344);
   U345 : nand2 port map( a => n343, b => n345, outb => n300);
   U346 : xor2 port map( a => n320, b => n321, outb => n343);
   U347 : inv port map( inb => n282, outb => n321);
   U348 : aoi12 port map( b => n346, c => n347, a => n87, outb => n316);
   U349 : nor2 port map( a => n329, b => n328, outb => n334);
   U350 : nor2 port map( a => n348, b => n349, outb => n329);
   U351 : inv port map( inb => n350, outb => n349);
   U352 : inv port map( inb => n213, outb => n331);
   U353 : oai22 port map( a => n216, b => n214, c => q3_8_port, d => n351, outb
                           => n213);
   U354 : inv port map( inb => n352, outb => n351);
   U355 : nand2 port map( a => n214, b => n216, outb => n352);
   U356 : inv port map( inb => n353, outb => n214);
   U357 : oai22 port map( a => n219, b => n217, c => q3_7_port, d => n354, outb
                           => n353);
   U358 : nor2 port map( a => n355, b => n356, outb => n354);
   U359 : inv port map( inb => n355, outb => n217);
   U360 : xor2 port map( a => n357, b => xin(7), outb => n355);
   U361 : inv port map( inb => n356, outb => n219);
   U362 : oai22 port map( a => n222, b => n220, c => q3_6_port, d => n358, outb
                           => n356);
   U363 : nor2 port map( a => n359, b => n360, outb => n358);
   U364 : inv port map( inb => n220, outb => n359);
   U365 : xor2 port map( a => n361, b => n362, outb => n220);
   U366 : nand2 port map( a => xin(0), b => n363, outb => n361);
   U367 : inv port map( inb => n360, outb => n222);
   U368 : oai22 port map( a => n225, b => n223, c => q3_5_port, d => n364, outb
                           => n360);
   U369 : nor2 port map( a => n365, b => n366, outb => n364);
   U370 : inv port map( inb => n365, outb => n223);
   U371 : xor2 port map( a => n367, b => n368, outb => n365);
   U372 : nand2 port map( a => n369, b => n370, outb => n367);
   U373 : inv port map( inb => n366, outb => n225);
   U374 : oai22 port map( a => n228, b => n226, c => q3_4_port, d => n371, outb
                           => n366);
   U375 : nor2 port map( a => n372, b => n373, outb => n371);
   U376 : inv port map( inb => n226, outb => n372);
   U377 : xor2 port map( a => n369, b => n370, outb => n226);
   U378 : inv port map( inb => n373, outb => n228);
   U379 : oai22 port map( a => n231, b => n229, c => q3_3_port, d => n374, outb
                           => n373);
   U380 : inv port map( inb => n375, outb => n374);
   U381 : nand2 port map( a => n229, b => n231, outb => n375);
   U382 : xor2 port map( a => n376, b => n377, outb => n229);
   U383 : nand2 port map( a => xin(0), b => n45, outb => n376);
   U384 : inv port map( inb => n378, outb => n231);
   U385 : oai22 port map( a => n234, b => n232, c => q3_2_port, d => n379, outb
                           => n378);
   U386 : nor2 port map( a => n380, b => n381, outb => n379);
   U387 : inv port map( inb => n380, outb => n232);
   U388 : xor2 port map( a => xin(0), b => n45, outb => n380);
   U389 : inv port map( inb => n381, outb => n234);
   U390 : nand2 port map( a => q3_1_port, b => xin(0), outb => n381);
   U391 : nor2 port map( a => n382, b => n328, outb => n216);
   U392 : nor3 port map( a => n383, b => n30, c => n357, outb => n328);
   U393 : inv port map( inb => n384, outb => n382);
   U394 : oai12 port map( b => n30, c => n357, a => n383, outb => n384);
   U395 : xor2 port map( a => n350, b => n348, outb => n383);
   U396 : xor2 port map( a => n325, b => n327, outb => n350);
   U397 : aoi12 port map( b => n385, c => n386, a => n45, outb => n327);
   U398 : xor2 port map( a => n387, b => n347, outb => n325);
   U399 : inv port map( inb => n388, outb => n347);
   U400 : xor2 port map( a => n338, b => n339, outb => n388);
   U401 : xor2 port map( a => n341, b => n345, outb => n339);
   U402 : oai12 port map( b => n282, c => n78, a => n320, outb => n345);
   U403 : oai12 port map( b => n389, c => xin(5), a => xin(4), outb => n341);
   U404 : nand2 port map( a => n390, b => n391, outb => n338);
   U405 : nand2 port map( a => xin(2), b => n346, outb => n387);
   U406 : nand3 port map( a => n392, b => n393, c => n394, outb => n346);
   U407 : oai12 port map( b => n395, c => n396, a => n348, outb => n357);
   U408 : nand2 port map( a => n395, b => n396, outb => n348);
   U409 : xor2 port map( a => n386, b => n397, outb => n396);
   U410 : nand2 port map( a => n385, b => xin(1), outb => n397);
   U411 : nand3 port map( a => n398, b => n399, c => n400, outb => n385);
   U412 : xor2 port map( a => n392, b => n401, outb => n386);
   U413 : nand2 port map( a => n393, b => n394, outb => n401);
   U414 : xor2 port map( a => n391, b => n390, outb => n392);
   U415 : aoi12 port map( b => n81, c => n402, a => n84, outb => n390);
   U416 : xor2 port map( a => n403, b => n389, outb => n391);
   U417 : aoi12 port map( b => n78, c => n284, a => n282, outb => n389);
   U418 : nor2 port map( a => n78, b => n284, outb => n282);
   U419 : nor2 port map( a => n81, b => xin(5), outb => n403);
   U420 : aoi12 port map( b => n363, c => n362, a => n103, outb => n395);
   U421 : xor2 port map( a => n404, b => n399, outb => n362);
   U422 : xor2 port map( a => n394, b => n393, outb => n399);
   U423 : xor2 port map( a => n405, b => n402, outb => n393);
   U424 : xor2 port map( a => n78, b => xin(4), outb => n402);
   U425 : nand2 port map( a => xin(3), b => n81, outb => n405);
   U426 : aoi12 port map( b => n84, c => n406, a => n87, outb => n394);
   U427 : nand2 port map( a => n400, b => n398, outb => n404);
   U428 : nand3 port map( a => n370, b => n368, c => n369, outb => n363);
   U429 : aoi12 port map( b => n45, c => n377, a => n103, outb => n369);
   U430 : xor2 port map( a => xin(1), b => n87, outb => n377);
   U431 : xor2 port map( a => n398, b => n400, outb => n368);
   U432 : aoi12 port map( b => n87, c => n407, a => n45, outb => n400);
   U433 : xor2 port map( a => n408, b => n406, outb => n398);
   U434 : xor2 port map( a => n84, b => xin(4), outb => n406);
   U435 : nand2 port map( a => xin(2), b => n84, outb => n408);
   U436 : xor2 port map( a => n409, b => n407, outb => n370);
   U437 : xor2 port map( a => n84, b => xin(2), outb => n407);
   U438 : nand2 port map( a => xin(1), b => n87, outb => n409);
   U439 : xor2 port map( a => n410, b => n139, outb => add2_9_port);
   U440 : xor2 port map( a => q2_9_port, b => n411, outb => n410);
   U441 : xor2 port map( a => n412, b => n142, outb => add2_8_port);
   U442 : xor2 port map( a => q2_8_port, b => n413, outb => n412);
   U443 : xor2 port map( a => n414, b => n415, outb => add2_7_port);
   U444 : xor2 port map( a => q2_7_port, b => n146, outb => n415);
   U445 : xor2 port map( a => n147, b => n416, outb => add2_6_port);
   U446 : xor2 port map( a => q2_6_port, b => n417, outb => n416);
   U447 : xor2 port map( a => n150, b => n418, outb => add2_5_port);
   U448 : xor2 port map( a => q2_5_port, b => n419, outb => n418);
   U449 : xor2 port map( a => n153, b => n420, outb => add2_4_port);
   U450 : xor2 port map( a => q2_4_port, b => n421, outb => n420);
   U451 : xor2 port map( a => n422, b => n423, outb => add2_3_port);
   U452 : xor2 port map( a => q2_3_port, b => xin(2), outb => n423);
   U453 : xor2 port map( a => n424, b => n425, outb => add2_2_port);
   U454 : xor2 port map( a => q2_2_port, b => n45, outb => n425);
   U455 : xor2 port map( a => q2_1_port, b => xin(0), outb => add2_1_port);
   U456 : xor2 port map( a => n426, b => n427, outb => add2_15_port);
   U457 : xor2 port map( a => q2_15_port, b => n162, outb => n427);
   U458 : aoi22 port map( a => n428, b => n429, c => n430, d => n166, outb => 
                           n426);
   U459 : nand2 port map( a => n431, b => n162, outb => n428);
   U460 : xor2 port map( a => n431, b => n432, outb => add2_14_port);
   U461 : xor2 port map( a => n429, b => n166, outb => n432);
   U462 : inv port map( inb => q2_14_port, outb => n429);
   U463 : inv port map( inb => n430, outb => n431);
   U464 : aoi22 port map( a => n162, b => n433, c => n434, d => q2_13_port, 
                           outb => n430);
   U465 : nand2 port map( a => n435, b => n166, outb => n434);
   U466 : xor2 port map( a => n433, b => n436, outb => add2_13_port);
   U467 : xor2 port map( a => q2_13_port, b => n162, outb => n436);
   U468 : inv port map( inb => n435, outb => n433);
   U469 : oai22 port map( a => n162, b => n437, c => q2_12_port, d => n438, 
                           outb => n435);
   U470 : nor2 port map( a => n166, b => n439, outb => n438);
   U471 : inv port map( inb => n162, outb => n166);
   U472 : xor2 port map( a => n437, b => n440, outb => add2_12_port);
   U473 : xor2 port map( a => q2_12_port, b => n162, outb => n440);
   U474 : aoi12 port map( b => n441, c => n253, a => n30, outb => n162);
   U475 : inv port map( inb => n439, outb => n437);
   U476 : oai22 port map( a => n442, b => n178, c => q2_11_port, d => n443, 
                           outb => n439);
   U477 : nor2 port map( a => n180, b => n444, outb => n443);
   U478 : inv port map( inb => n178, outb => n180);
   U479 : xor2 port map( a => n178, b => n445, outb => add2_11_port);
   U480 : xor2 port map( a => q2_11_port, b => n442, outb => n445);
   U481 : inv port map( inb => n444, outb => n442);
   U482 : oai22 port map( a => n446, b => n184, c => q2_10_port, d => n447, 
                           outb => n444);
   U483 : nor2 port map( a => n186, b => n448, outb => n447);
   U484 : xor2 port map( a => n253, b => n441, outb => n178);
   U485 : oai12 port map( b => n449, c => n450, a => n451, outb => n441);
   U486 : nand2 port map( a => n283, b => n322, outb => n253);
   U487 : inv port map( inb => n452, outb => n283);
   U488 : xor2 port map( a => n184, b => n453, outb => add2_10_port);
   U489 : xor2 port map( a => q2_10_port, b => n446, outb => n453);
   U490 : inv port map( inb => n448, outb => n446);
   U491 : oai22 port map( a => n454, b => n190, c => q2_9_port, d => n455, outb
                           => n448);
   U492 : nor2 port map( a => n139, b => n411, outb => n455);
   U493 : inv port map( inb => n139, outb => n190);
   U494 : xor2 port map( a => n456, b => n457, outb => n139);
   U495 : nor2 port map( a => n458, b => n459, outb => n456);
   U496 : inv port map( inb => n411, outb => n454);
   U497 : oai22 port map( a => n460, b => n193, c => q2_8_port, d => n461, outb
                           => n411);
   U498 : nor2 port map( a => n142, b => n413, outb => n461);
   U499 : inv port map( inb => n142, outb => n193);
   U500 : xor2 port map( a => n462, b => n463, outb => n142);
   U501 : nand2 port map( a => n464, b => n465, outb => n462);
   U502 : inv port map( inb => n413, outb => n460);
   U503 : oai22 port map( a => n146, b => n414, c => q2_7_port, d => n466, outb
                           => n413);
   U504 : nor2 port map( a => n197, b => n467, outb => n466);
   U505 : inv port map( inb => n467, outb => n414);
   U506 : oai22 port map( a => n417, b => n147, c => q2_6_port, d => n468, outb
                           => n467);
   U507 : nor2 port map( a => n199, b => n469, outb => n468);
   U508 : inv port map( inb => n147, outb => n199);
   U509 : xor2 port map( a => n470, b => n471, outb => n147);
   U510 : inv port map( inb => n469, outb => n417);
   U511 : oai22 port map( a => n419, b => n150, c => q2_5_port, d => n472, outb
                           => n469);
   U512 : nor2 port map( a => n202, b => n473, outb => n472);
   U513 : inv port map( inb => n150, outb => n202);
   U514 : xor2 port map( a => n474, b => n475, outb => n150);
   U515 : inv port map( inb => n473, outb => n419);
   U516 : oai22 port map( a => n421, b => n153, c => q2_4_port, d => n476, outb
                           => n473);
   U517 : nor2 port map( a => n205, b => n477, outb => n476);
   U518 : inv port map( inb => n153, outb => n205);
   U519 : xor2 port map( a => n103, b => n84, outb => n153);
   U520 : inv port map( inb => n477, outb => n421);
   U521 : oai22 port map( a => xin(2), b => n422, c => q2_3_port, d => n478, 
                           outb => n477);
   U522 : nor2 port map( a => n87, b => n479, outb => n478);
   U523 : inv port map( inb => n479, outb => n422);
   U524 : oai22 port map( a => xin(1), b => n480, c => q2_2_port, d => n481, 
                           outb => n479);
   U525 : nor2 port map( a => n45, b => n424, outb => n481);
   U526 : inv port map( inb => n424, outb => n480);
   U527 : nand2 port map( a => q2_1_port, b => xin(0), outb => n424);
   U528 : inv port map( inb => n197, outb => n146);
   U529 : nand2 port map( a => n482, b => n465, outb => n197);
   U530 : oai12 port map( b => n471, c => n470, a => n483, outb => n482);
   U531 : inv port map( inb => n186, outb => n184);
   U532 : xor2 port map( a => n450, b => n484, outb => n186);
   U533 : nor2 port map( a => n449, b => n485, outb => n484);
   U534 : inv port map( inb => n451, outb => n485);
   U535 : nand2 port map( a => n486, b => n487, outb => n451);
   U536 : nor2 port map( a => n488, b => n489, outb => n449);
   U537 : xor2 port map( a => n490, b => n452, outb => n488);
   U538 : oai12 port map( b => n458, c => n459, a => n457, outb => n450);
   U539 : xor2 port map( a => n486, b => n487, outb => n457);
   U540 : xor2 port map( a => n281, b => n489, outb => n487);
   U541 : nor2 port map( a => n322, b => n81, outb => n489);
   U542 : aoi12 port map( b => n30, c => n78, a => n452, outb => n281);
   U543 : nor2 port map( a => n78, b => n30, outb => n452);
   U544 : inv port map( inb => n491, outb => n486);
   U545 : nor2 port map( a => n492, b => n493, outb => n459);
   U546 : aoi12 port map( b => n465, c => n464, a => n463, outb => n458);
   U547 : xor2 port map( a => n494, b => n492, outb => n463);
   U548 : inv port map( inb => n493, outb => n494);
   U549 : oai12 port map( b => n495, c => n496, a => n491, outb => n493);
   U550 : nand2 port map( a => n495, b => n496, outb => n491);
   U551 : xor2 port map( a => n322, b => n81, outb => n496);
   U552 : nand2 port map( a => xin(6), b => xin(7), outb => n322);
   U553 : nor2 port map( a => n84, b => n284, outb => n495);
   U554 : inv port map( inb => n490, outb => n284);
   U555 : aoi22 port map( a => n497, b => n498, c => n499, d => xin(7), outb =>
                           n464);
   U556 : nand2 port map( a => n500, b => n501, outb => n499);
   U557 : inv port map( inb => n501, outb => n498);
   U558 : inv port map( inb => n500, outb => n497);
   U559 : inv port map( inb => n502, outb => n465);
   U560 : nor3 port map( a => n471, b => n483, c => n470, outb => n502);
   U561 : oai12 port map( b => n503, c => n504, a => n500, outb => n470);
   U562 : xor2 port map( a => n501, b => n505, outb => n483);
   U563 : xor2 port map( a => n30, b => n500, outb => n505);
   U564 : nand2 port map( a => n503, b => n504, outb => n500);
   U565 : xor2 port map( a => xin(5), b => xin(2), outb => n504);
   U566 : nor2 port map( a => n81, b => n45, outb => n503);
   U567 : oai12 port map( b => n506, c => n507, a => n492, outb => n501);
   U568 : nand2 port map( a => n506, b => n507, outb => n492);
   U569 : xor2 port map( a => xin(3), b => n490, outb => n507);
   U570 : oai12 port map( b => xin(6), c => n30, a => n320, outb => n490);
   U571 : nand2 port map( a => xin(6), b => n30, outb => n320);
   U572 : nor2 port map( a => n78, b => n87, outb => n506);
   U573 : nand2 port map( a => n474, b => n475, outb => n471);
   U574 : xor2 port map( a => xin(4), b => xin(1), outb => n475);
   U575 : nor2 port map( a => n84, b => n103, outb => n474);
   U576 : xor2 port map( a => n508, b => n509, outb => add1_9_port);
   U577 : xor2 port map( a => q1_9_port, b => xin(6), outb => n509);
   U578 : xor2 port map( a => n510, b => n511, outb => add1_8_port);
   U579 : xor2 port map( a => q1_8_port, b => xin(5), outb => n511);
   U580 : xor2 port map( a => n512, b => n513, outb => add1_7_port);
   U581 : xor2 port map( a => q1_7_port, b => xin(4), outb => n513);
   U582 : xor2 port map( a => n514, b => n515, outb => add1_6_port);
   U583 : xor2 port map( a => q1_6_port, b => xin(3), outb => n515);
   U584 : xor2 port map( a => n516, b => n517, outb => add1_5_port);
   U585 : xor2 port map( a => q1_5_port, b => xin(2), outb => n517);
   U586 : xor2 port map( a => n518, b => n519, outb => add1_4_port);
   U587 : xor2 port map( a => q1_4_port, b => n45, outb => n519);
   U588 : inv port map( inb => n520, outb => add1_3_port);
   U589 : aoi12 port map( b => n103, c => q1_3_port, a => n521, outb => n520);
   U590 : xor2 port map( a => n522, b => n523, outb => add1_15_port);
   U591 : xor2 port map( a => q1_15_port, b => xin(7), outb => n523);
   U592 : oai22 port map( a => n30, b => n524, c => q1_14_port, d => n525, outb
                           => n522);
   U593 : nor2 port map( a => n526, b => xin(7), outb => n525);
   U594 : inv port map( inb => n526, outb => n524);
   U595 : xor2 port map( a => n526, b => n527, outb => add1_14_port);
   U596 : xor2 port map( a => q1_14_port, b => xin(7), outb => n527);
   U597 : aoi22 port map( a => n30, b => n528, c => n529, d => q1_13_port, outb
                           => n526);
   U598 : nand2 port map( a => n530, b => xin(7), outb => n529);
   U599 : inv port map( inb => n530, outb => n528);
   U600 : xor2 port map( a => n530, b => n531, outb => add1_13_port);
   U601 : xor2 port map( a => q1_13_port, b => xin(7), outb => n531);
   U602 : oai22 port map( a => n30, b => n532, c => q1_12_port, d => n533, outb
                           => n530);
   U603 : nor2 port map( a => n534, b => xin(7), outb => n533);
   U604 : inv port map( inb => n534, outb => n532);
   U605 : xor2 port map( a => n534, b => n535, outb => add1_12_port);
   U606 : xor2 port map( a => q1_12_port, b => xin(7), outb => n535);
   U607 : aoi22 port map( a => n30, b => n536, c => n537, d => q1_11_port, outb
                           => n534);
   U608 : nand2 port map( a => n538, b => xin(7), outb => n537);
   U609 : inv port map( inb => n538, outb => n536);
   U610 : xor2 port map( a => n538, b => n539, outb => add1_11_port);
   U611 : xor2 port map( a => q1_11_port, b => xin(7), outb => n539);
   U612 : oai22 port map( a => n30, b => n540, c => q1_10_port, d => n541, outb
                           => n538);
   U613 : nor2 port map( a => n542, b => xin(7), outb => n541);
   U614 : inv port map( inb => n542, outb => n540);
   U615 : inv port map( inb => xin(7), outb => n30);
   U616 : xor2 port map( a => n542, b => n543, outb => add1_10_port);
   U617 : xor2 port map( a => q1_10_port, b => xin(7), outb => n543);
   U618 : aoi22 port map( a => n75, b => n544, c => n545, d => q1_9_port, outb 
                           => n542);
   U619 : nand2 port map( a => xin(6), b => n508, outb => n545);
   U620 : inv port map( inb => n508, outb => n544);
   U621 : aoi22 port map( a => n78, b => n546, c => n547, d => q1_8_port, outb 
                           => n508);
   U622 : nand2 port map( a => xin(5), b => n510, outb => n547);
   U623 : inv port map( inb => n510, outb => n546);
   U624 : aoi22 port map( a => n81, b => n548, c => n549, d => q1_7_port, outb 
                           => n510);
   U625 : nand2 port map( a => xin(4), b => n512, outb => n549);
   U626 : inv port map( inb => n512, outb => n548);
   U627 : aoi22 port map( a => n84, b => n550, c => n551, d => q1_6_port, outb 
                           => n512);
   U628 : nand2 port map( a => xin(3), b => n514, outb => n551);
   U629 : inv port map( inb => n514, outb => n550);
   U630 : aoi22 port map( a => n87, b => n552, c => n553, d => q1_5_port, outb 
                           => n514);
   U631 : nand2 port map( a => xin(2), b => n516, outb => n553);
   U632 : inv port map( inb => n516, outb => n552);
   U633 : aoi22 port map( a => n45, b => n518, c => n554, d => q1_4_port, outb 
                           => n516);
   U634 : nand2 port map( a => xin(1), b => n521, outb => n554);
   U635 : inv port map( inb => n521, outb => n518);
   U636 : nor2 port map( a => n103, b => q1_3_port, outb => n521);
   U637 : inv port map( inb => xin(0), outb => n103);
   U638 : inv port map( inb => xin(1), outb => n45);
   U639 : inv port map( inb => xin(2), outb => n87);
   U640 : inv port map( inb => xin(3), outb => n84);
   U641 : inv port map( inb => xin(4), outb => n81);
   U642 : inv port map( inb => xin(5), outb => n78);
   U643 : inv port map( inb => xin(6), outb => n75);

end SYN_Behavioral;
 

The fault is your private SIGNED declaration which is conflicting with ieee.numeric_std
Code:
type SIGNED is array (INTEGER range <>) of std_logic;

Delete the declaration and import numeric_std instead.
 

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