VHDL code to count leading number of 0s.

[Rimon Selim]

I want to design a circuit with sequential coding to count the number of leading zeros, must be sequential.

Example 00001101 has 4. Example 00000001 has 7.

Thank you for the help.

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Code VHDL - [expand]
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LIBRARY ieee ;
USE ire . std_logic_1164 . all;
-- -----------------------
ENTITY leading_zeros IS
PORT ( data : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0);
zeros : OUT INTEGER range 0 to 8);
END ENTITY ;
-- -----------------------

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[K-J]

Next steps for you would be:
- Write the architecture.
- Simulate the design
- If the output does not match what you intend AND you have attempted to debug the problem then you should:

- Post the code you have
- Write up a description of what the problem you're observing (Hint: "It's not working" will not produce any useful feedback from the group)

Good luck on your assignment.

Kevin Jennings

 

[FvM]

If "sequential" means actually a sequential circuit, counting sequentially in time, there must be a clock and probably a start signal. Or do you mean a sequential description of an asynchronous circuit, e.g. using a for loop?

- - - Updated - - -

Some previous threads about leading '0'/ leading '1' detectors:
https://www.edaboard.com/threads/50923/
https://www.edaboard.com/threads/201958/

Also notice the links under "Similar Threads" below.