vhdl code to call data from .txt file

anyone know how to call data from .txt using vhdl code?

i have develop a rom that store data like below....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_signed.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sss is
Port (
clk : in STD_LOGIC;
e : in STD_LOGIC;
r : in STD_LOGIC;
data_out : out STD_LOGIC_vector (7 downto 0)
);
end entity sss;

architecture rtl of sss is

signal i : integer range 0 to 999:=0;
signal enable : std_logic:='0';
signal data : std_logic_vector (7 downto 0);

BEGIN

process (e)
begin
if e'event and e = '1' then
enable <= '1';
end if;
end process;

process ( clk)
begin
if rising_edge (clk) then
if (enable = '1') then
i <= i + 1;
end if;
end if;
end process;

process (clk)
begin
if rising_edge (clk) then
case i is
when 0 => data <= "10111100"; --value
when 1 => data <= "11011001";
when 2 => data <= "00000111";
when 3 => data <= "10101000";
when 4 => data <= "10101001";
when 5 => data <= "10101000";
when 6 => data <= "10101011";
when 7 => data <= "10110010";
-- .... until 1000
end case;
end if;
end process;

i have create .txt file that have the value in a column. how can i call the .text file to put in my rom. so that i must not fill 1000 case address for 1000 value like above code. please help.urgent.

Hi,

-- extra packages:
library std;
use std.textio.all;
use ieee.std_logic_textio.all;

-- file declaration (VHDL 93 syntax) in architecture:
file fin : text open read_mode is "c:/temp/input_file.txt";

-- read file contents somewhere in process:
process....
variable inp_line : line;
begin
---
while not endfile (fin) loop
readline(fin, inp_line);
read(inp_line, column1);
read(inp_line, column2); -- when you have multiple columns
...
end loop;

when you use hex values in your columns you can use hread(inp_line, column1);

Devas

Does Xilinx support textio library? I'm only aware of support with simulators, e.g. ModelSim.

as fvm said, make sure that xilinx supports the textio library...
i only tried it in testbenches on modelsim

Hi,

Oke, my mistake I thought you want to use it for simulation.

When you generate your ROM using CoreGenerator you can use a coe file to initialize the ROM code.
When you have written your own VHDL code to model the ROM I guess the only way to initialize the ROM, to use in the Xilinx environment, is by copying your text file inside the VHDL code.

Devas

did you mean i have no other choice. i must insert 1000 value and 1000 address in my code?

I think, the code is intended to infer a ROM table? Most tools have means to enter ROM data from a file, e.g. Altera supports *.hex,
both in synthesized code and ModelSim simulation. Nobody wants to write 1000 case statements! But I don't know what's the
best way with Xilinx ISE.

I am upload this https://opencores.org/project,workwithfiles

I think that make test blocks with ce and clk this is very good for future arhitecture of whole project