VHDL code - serious warnings with simple model

[Yoking]

isplever logocal net has no load

The attachment is a test vhdl code project.Its very simple,but it has serious waring under isplever 7.0! I dont know how it generated, so you can compile under ise or
quartus to check out the reason.

I just wonder is it from VHDL code problem or the software setings problem..

Running DRC...
WARNING - ngdbuild: logical net 'clk' has no load
WARNING - ngdbuild: logical net 'sign1' has no load
WARNING - ngdbuild: logical net 'sign2' has no load
WARNING - ngdbuild: logical net 'sign3' has no load
WARNING - ngdbuild: logical net 'sign4' has no load
WARNING - ngdbuild: DRC complete with 5 warnings

 

[FvM]

isplever ngdbuild has no load

I guess, the warnings are caused by an invalid clkcnt component, that has most of it's logic removed in synthesis. Thus the output signals are undriven and nothing depends on the input signals.

One basic error (there may be more) in clkcnt is to count up a variable in a combinational process (without an edge sensitive condition). This doesn't work in synthesizable HDL code. I suggest to design an operational clkcnt component first.

 

[Yoking]

isplever warning - ngdbuild: logical net

I guess, the warnings are caused by an invalid clkcnt component, that has most of it's logic removed in synthesis. Thus the output signals are undriven and nothing depends on the input signals.

One basic error (there may be more) in clkcnt is to count up a variable in a combinational process (without an edge sensitive condition). This doesn't work in synthesizable HDL code. I suggest to design an operational clkcnt component first.

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im very sorry for that basic error i've made!

I just dont wanna mislead other people,so delete the file!
thanks for you concern!
I have to learn more...........................
Oh,My god.whats happenning?