#### rara801

##### Newbie level 2

ello guys...

i'm having a problem with the vhdl coding...

this my coding for 8bit wide 2-to-1 multiplexer....i need to connect the switches to red light LEDR and the the output to green light LEDG in de2 board but the problem the interface object "SW" of mode out cannot be read. Change object mode to buffer. how to solve this problem

i'm having a problem with the vhdl coding...

this my coding for 8bit wide 2-to-1 multiplexer....i need to connect the switches to red light LEDR and the the output to green light LEDG in de2 board but the problem the interface object "SW" of mode out cannot be read. Change object mode to buffer. how to solve this problem

Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 library ieee; use ieee.std_logic_1164.all; entity part2_2 is PORT( x:IN STD_LOGIC_VECTOR(7 DOWNTO 0); y:IN STD_LOGIC_VECTOR(7 DOWNTO 0); S:IN STD_LOGIC; SW:OUT STD_LOGIC_VECTOR(17 DOWNTO 0); LEDR :OUT STD_LOGIC_VECTOR (17 DOWNTO 0); LEDG :OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); end part2_2; architecture Behavior of part2_2 is BEGIN PROCESS(S) begin if S ='0' then LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7)); LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6)); LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5)); LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4)); LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3)); LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2)); LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1)); LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0)); ELSIF SW(17) ='1' then LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7)); LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6)); LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5)); LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4)); LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3)); LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2)); LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1)); LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0)); end if; SW(17)<=S; LEDR(0) <= x(0); LEDR(1) <= x(1); LEDR(2) <= x(2); LEDR(3) <= x(3); LEDR(4) <= x(4); LEDR(5) <= x(5); LEDR(6) <= x(6); LEDR(7) <= x(7); LEDR(8) <= y(0); LEDR(9) <= y(1); LEDR(10) <= y(2); LEDR(11) <= y(3); LEDR(12) <= y(4); LEDR(13) <= y(5); LEDR(14) <= y(6); LEDR(15) <= y(7); LEDR(0) <= SW(0); LEDR(1) <= SW(1); LEDR(2) <= SW(2); LEDR(3) <= SW(3); LEDR(4) <= SW(4); LEDR(5) <= SW(5); LEDR(6) <= SW(6); LEDR(7) <= SW(7); LEDR(8) <= SW(8); LEDR(9) <= SW(9); LEDR(10) <= SW(10); LEDR(11) <= SW(11); LEDR(12) <= SW(12); LEDR(13) <= SW(13); LEDR(14) <= SW(14); LEDR(15) <= SW(15); LEDR(17) <= SW(17); end PROCESS; end Behavior;

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