VHDL Code of UART on sparan 3e kit

[missbirdie]

vhdl code for uart

Hello
I need help in the following VHDL code .. i'm not so good in VHDL so I need someone to explain to me how does this code achieve the UART transmitter plz

VHDL Code:
========
entity uart_tx is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
tx_data : in STD_LOGIC_VECTOR (7 downto 0);
ready : in STD_LOGIC;
tdre : out STD_LOGIC;
TxD : out STD_LOGIC);
end uart_tx;
architecture uart_tx of uart_tx is
type state_type is (mark, start, delay, shift, stop);
signal state: state_type;
signal txbuff: STD_LOGIC_VECTOR (7 downto 0);
signal baud_count: STD_LOGIC_VECTOR (11 downto 0);
signal bit_count: STD_LOGIC_VECTOR (3 downto 0);
constant bit_time: STD_LOGIC_VECTOR (11 downto 0) := X"A28";
begin
uart2: process(clk, clr, ready)
begin
if clr = '1' then
state <= mark;
txbuff <= "00000000";
baud_count <= X"000";
bit_count <= "0000";
TxD <= '1';
elsif (clk'event and clk = '1') then
case state is
when mark => -- wait for ready
bit_count <= "0000";
tdre <= '1';
if ready = '0' then
state <= mark;
txbuff <= tx_data;
else
baud_count <= X"000";
state <= start; -- go to start
end if;
when start => -- output start bit
baud_count <= X"000";
TxD <= '0';
tdre <= '0';
state <= delay; -- go to delay
when delay => -- wait bit time
tdre <= '0';
if baud_count >= bit_time then
baud_count <= X"000";
if bit_count < 8 then -- if not done
state <= shift; -- go to shift
else -- else
state <= stop; -- go to stop
end if;
else
baud_count <= baud_count + 1;
state <= delay; -- stay in delay
end if;
when shift => -- get next bit
tdre <= '0';
TxD <= txbuff(0);
txbuff(6 downto 0) <= txbuff(7 downto 1);
bit_count <= bit_count + 1;
state <= delay;
when stop => -- stop bit
tdre <='0';
TxD <= '1';
if baud_count >= bit_time then
baud_count <= X"000";
state <= mark;
else
baud_count <= baud_count + 1;
state <= stop;
end if;
end case;
end if;
end process uart2;
end uart_tx;

Added after 35 minutes:

If this is the block diagram of the code.. how can i connect the tdre & ready ?? I mean aren't they signal for handshaking ??

 

[FvM]

uart vhdl code

Personally, I would designate a start input txstart rather than ready, but the present naming may be meaningful in a particular design.

Actually, the UART has an input to trigger transmission and a status output to signal end of transmission, that should be all you need to use it in a design. So what's the problem? Of course we can't about your application, but normally, there must be a source of data and an instance that requests transmission of data.

 

[abhi_459]

vhdl uart

hi..
plz read the book by Roth

 

[missbirdie]

vhdl code for usart

Actually i understood the code finally & i think that the tdre should be connected to the Data terminal ready of the pc & the ready with Data set ready signal from the pc..my question is how can i connect these input to specific pins in the RS232 port ?? In the FPGA user guide only the sent & receive pins are shown.

I need to send some data from the FPGA to the pc.. so i wrote this code & convert it into schematic & connect it with the rest of the design but in assigning the pin numbers how can i connect a sigle pin of the serial port ?

 

[FvM]

uart vhdl

I wonder, what some data means in your application. If it's more than repeating a character endlessly, then there must be a start of transmission signal to the UART. It's O.K.to connect only TxD to the PC, but the ready and trde have to be connected in your FPGA design internally.

 

[missbirdie]

vhdl uart code

I just wanna send a stream of bits.. & how can i connect the tdre & ready internally ???

 

[FvM]

uart transmitter vhdl

I think, simply connecting the two signals causes the UART to send repeatedly. Why don't you try?
P.S: You may need to use a wire symbol to connect two nets in schematic entry.

 

[missbirdie]

vhdl code for uart

thanks 'll try this.. but won't i need Picoblaze ???

Added after 2 hours 48 minutes:

isn't it in this case like a shift register ???

 

[FvM]

vhdl baud generator

isn't it in this case like a shift register ???

Any UART is a shiftregister with a baud generator and some control logic.

but won't i need Picoblaze ???

May be you need Picoblaze in your design, but I can't know from what you have told so far.

I just wanna send a stream of bits...

This is achieved by the present design.

 

[missbirdie]

vhdl uart baud generator

but how an i connect tdre to ready ?? isn't ready supposed to be 0 initially for the code ?? how can i do this & it's an internal signal ??

 

[FvM]

vhdl code for uart transmitter

isn't ready supposed to be 0 initially for the code ??

No, why?

 

[missbirdie]

vhdl code and transmission data

yeah u were right i even removed them & it worked
but i have one more question it's said that the baudrate is 9600 from the instruction :

constant bit_time: STD_LOGIC_VECTOR (11 downto 0) := X"A28";

& that X"A28" represents 9600 but actually i can't get it.. what about 115200 bps how can i change this code to fit it ??

P.S I know that i can change the PC baud rate but this is not what i want.. i wanna change the baud rate in this code to 115200

 

[FvM]

115200bps uart clk

It depends on your clock frequency. "A28" (2600) is for a clock frequency of 25 MHz. Just set the constant to Fclk/Baud - 1. It may be necessary to adjust the baud_counter word length.

 

[missbirdie]

uart baud vhdl

how can i change it to 115200 bps ??

Added after 5 hours 5 minutes:

but won't it non accurate division.. i mean isn't the baud rate value should be sharp !! with no fractions !!

 

[FvM]

uart vhdl code 8 bit

I'm using a calculator generally, it tells 216. So why not trying with this value?

I'dont understand what you mean with a sharp baud rate, I never heard of such a thing. Actually, the baud rate has a certain frequency error. That's no problem, also a PC has, it's using 24 MHz/(13*16) in most cases, which is 115385 baud. A 1 or 2 % deviation can be always tolerated with an UART, but it's much less here.

 

[suryakumari]

VHDL Code of UART

can any1 tel d operation of vhdl code for uart receiver