sailakshmi
Newbie level 2
vhdl code for 32 bit counter so please help me.......................................vhdl code
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library IEEE;
use IEEE.std_logic_1164.all;
entity cntr is
generic(left : natural := 31;
prop : time := 100 ps);
port (clk : in std_logic;
load : in std_logic;
in_load : in std_logic_vector (left downto 0);
output : out std_logic_vector (left downto 0) );
end entity cntr_g;
architecture behavior of cntr is
begin
cntr: process(clk, load)
variable counter : std_logic_vector(left downto 0);
variable carry : std_logic;
variable tcarry : std_logic;
begin
if load='1' then
counter := in_load;
output <= in_load;
elsif clk'event and clk='1' then
carry := '1';
for i in 0 to left loop
tcarry := counter(i) and carry;
counter(i) := counter(i) xor carry;
carry := tcarry;
end loop;
output <= counter after prop;
end if;
end process cntr;
end architecture behavior;