VHDL code modification help!

[wallywall]

hello, i wrote a code to convert bcd to 7 segment. i want to simulate my code in TINA but when the block diagram is displayed, it only has 1 input and 1 output instead of 4 inputs and 7 ouputs, i know this is because i used logic vectors but how do i modify my code so that the block diagram shows the 4 inputs and 7 outputs? my code is below

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY BCD IS
PORT (
          bcd : In STD_LOGIC_VECTOR (3 DOWNTO 0);
          sevenseg   : OUT STD_LOGIC_VECTOR ( 1 TO 7));
END BCD;

ARCHITECTURE Behavior OF BCD IS
BEGIN
	PROCESS (bcd)
	BEGIN
		CASE bcd IS				   --abcdefg
			 When "0000" => sevenseg <= "0000001";
			 When "0001" => sevenseg <= "1001111";
			 When "0010" => sevenseg <= "0010010";
                                       When "0011" => sevenseg <= "0000110";
			 When "0100" => sevenseg <= "1001100";
			 When "0101" => sevenseg <= "0100100";
			 When "0110" => sevenseg <= "0100000";
			 When "0111" => sevenseg <= "0001111";
			 When "1000" => sevenseg <= "0000000";
			 When "1001" => sevenseg <= "0001100";
			 When OTHERS => sevenseg <= "1111111"; --NOTHING SHOWING
END CASE;
END PROCESS;
END BEHAVIOR;

 

[AdvaRes]

Hi,
Define your input and output seperately, thenn define a new variable using inputs by concatenation (the operator &)
here is one exemple:
https://stackoverflow.com/questions/209458/concatenating-bits-in-vhdl