VHDL code for storing 3 different values in memory.

[Ian Bond]

Hello,
I am doing a project which involves writing 3 64 bit signals in memory and reading them later. My code has a 64 bit data_in, a 64 bit data_out, clock, an address1 signal, address2, address3 signal, Output enable, write enable and read enable signals. The input is given through data_in and in the first clock cycle, the input must be stored in address1 and after reading address1, data_in is changed and now, it must be stored in address2. The same is the case for address3.

Basically, I am varying the input 3 times and all these 3 must be stored in 3 different memory locations. Can anyone help me with this please?

 

[arunbharathi.arasu]

Zip and post your code

 

[aruipksni]

Hello,
I am doing a project which involves writing 3 64 bit signals in memory and reading them later. My code has a 64 bit data_in, a 64 bit data_out, clock, an address1 signal, address2, address3 signal, Output enable, write enable and read enable signals. The input is given through data_in and in the first clock cycle, the input must be stored in address1 and after reading address1, data_in is changed and now, it must be stored in address2. The same is the case for address3.

Basically, I am varying the input 3 times and all these 3 must be stored in 3 different memory locations. Can anyone help me with this please?

what you need is to connect each input to a fifo.
then you need to arbitratre/mux beetween fifo outputs with a fast clock and write to memory.

 

[Ian Bond]

I attached the code for 32 bit input. If this works, I can extend it to 64 bits.

 

[TrickyDicky]

Why not test the testbench yourself, then convert it to 64 bits yourself?

 

[Ian Bond]

Why not test the testbench yourself, then convert it to 64 bits yourself?

I tried it. It was not working. Please suggest some changes.

 

[mrflibble]

Please suggest some changes.

Apply more effort. And oh I don't know, actually show what you did. That makes it easier to help you.

By which I mean your testbench + attempts at extending it to 64-bits.

 

[Ian Bond]

Apply more effort. And oh I don't know, actually show what you did. That makes it easier to help you.

By which I mean your testbench + attempts at extending it to 64-bits.

I am unable to get the output even for 32 bits. Please refer to the first post.

 

[mrflibble]

Please refer to the "do more work yourself" part. All I see is you plonk down a zip, and say "it doesn't do what I want. please help". Anyways, don't mind me. I am sure the others will have time to guide you through everything. I'll read the summary when it's done.

 

[aruipksni]

Please refer to the "do more work yourself" part. All I see is you plonk down a zip, and say "it doesn't do what I want. please help". Anyways, don't mind me. I am sure the others will have time to guide you through everything. I'll read the summary when it's done.

What about RTL drawing. In the 90's
We had to do RTL drawings
And timing design before allowed to do
Any VHDL coding.
I know time has changed. Now time to
Market is most important,
but VHDL
Is basically stayed the same. So why don'T
you start with RTL and then implement
It in VHDL.