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# VHDL code for simple calculator, CPU or uP anyone please??

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#### maejchi

##### Newbie level 1
dear all, i'm a student and doing a research on simple calculator, CPU or uP for my Computer Architecture (CA) assignments...CA is one of my course subject...thus, i desperately need your help on any coding/program which involves all three; simple calculator, CPU or uP ASAP....i have searched for a few weeks but managed to found lots of coding which i couldnot understand most of the coding involved...so guys please help me cause i'm at total loss right now...u guys could give me either coding or any reference (links or books) for those coding...thank you very much!!!

You are a student doing research on computer architecture but have problem understanding the code you find on internet?

How about trying to write a simple calculator or a processor yourself?

am sure it would take you far less than a few weeks to do.

Best regards,

hi there! thanks for your kind reply. i am actually a communication engineering student but i'm supposed to take computer architecture. unfortunately our labs are simple where the complex code so far is only ALU. i have a lot of trouble in understanding those coding are basically more based on antenna and microwave. i have tried to make a program but unfortunately there seemed to be error. i'm in a rush right now...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity calc1 is
Port ( Clk : in std_logic;
Switches : in std_logic_vector(7 downto 0);
Buttons : in std_logic_vector(6 downto 0);
Result : out std_logic_vector(7 downto 0));
end calc1;

architecture Behavioral of calc1 is
Signal Q0,Q1,Q2,Q3: std_logic_vector(7 downto 0) := (others=>'0');
Signal S: std_logic_vector(1 downto 0);
Signal S3S2S1S0: std_logic_vector(3 downto 0);
Signal D,B,T: std_logic_vector(7 downto 0);
signal Old_buttons: std_logic_vector(6 downto 0);
begin
T <= Switches;
B <= (others=>'0');
Result <= Q0;

One_puls_detector:
process( clk)
variable One_pulses: std_logic_vector(6 downto 0);
begin
if rising_edge( Clk) then
Old_buttons <= Buttons;
One_pulses := not Old_buttons and Buttons;
case One_pulses is
when "0000001" => S <= "01"; S3S2S1S0 <= "0000"; -- Enter
when "0000010" => S <= "10"; S3S2S1S0 <= "0000"; -- Pop
when "0000100" => S <= "11"; S3S2S1S0 <= "0001"; -- +
when "0001000" => S <= "11"; S3S2S1S0 <= "0010"; -- -
when "0010000" => S <= "11"; S3S2S1S0 <= "0100"; -- *
when "0100000" => S <= "11"; S3S2S1S0 <= "1000"; -- /
when "1000000" => S <= "11"; S3S2S1S0 <= "1111"; -- XOR
when others => S <= "00"; S3S2S1S0 <= "0000"; -- nop
end case;
end if;
end process;

The_RPN_Stack:
process( Clk)
begin
if rising_edge( Clk) then
case S is
When "00" => Null;
When "01" => Q3<=Q2; Q2<=Q1; Q1<=Q0; Q0<=T;
When "10" => Q0<=Q1; Q1<=Q2; Q2<=Q3; Q3<=B;
When "11" => Q0<=D; Q1<=Q2; Q2<=Q3; Q3<=B;
When others => Null;
end case;
end if;
end process;

ALU_process:
process( S3S2S1S0, Q1, Q0)
begin
case S3S2S1S0 is
when "0001" => D <= Q1+Q0;
when "0010" => D <= Q1-Q0;
when "0100" => D <= Q1(3 downto 0) * Q0(3 downto 0);
-- When "1000" => D <= Q1/Q0; -- This one tricky - make a ROM
when "1111" => D <= Q1 xor Q0;
when others => D <= (others=>'0');
end case;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity calc1 is
Port ( Clk : in std_logic;
Switches : in std_logic_vector(7 downto 0);
Buttons : in std_logic_vector(6 downto 0);
Result : out std_logic_vector(7 downto 0));
end calc1;

architecture Behavioral of calc1 is
Signal Q0,Q1,Q2,Q3: std_logic_vector(7 downto 0) := (others=>'0');
Signal S: std_logic_vector(1 downto 0);
Signal S3S2S1S0: std_logic_vector(3 downto 0);
Signal D,B,T: std_logic_vector(7 downto 0);
signal Old_buttons: std_logic_vector(6 downto 0);
begin
T <= Switches;
B <= (others=>'0');
Result <= Q0;

One_puls_detector:
process( clk)
variable One_pulses: std_logic_vector(6 downto 0);
begin
if rising_edge( Clk) then
Old_buttons <= Buttons;
One_pulses := not Old_buttons and Buttons;
case One_pulses is
when "0000001" => S <= "01"; S3S2S1S0 <= "0000"; -- Enter
when "0000010" => S <= "10"; S3S2S1S0 <= "0000"; -- Pop
when "0000100" => S <= "11"; S3S2S1S0 <= "0001"; -- +
when "0001000" => S <= "11"; S3S2S1S0 <= "0010"; -- -
when "0010000" => S <= "11"; S3S2S1S0 <= "0100"; -- *
when "0100000" => S <= "11"; S3S2S1S0 <= "1000"; -- /
when "1000000" => S <= "11"; S3S2S1S0 <= "1111"; -- XOR
when others => S <= "00"; S3S2S1S0 <= "0000"; -- nop
end case;
end if;
end process;

The_RPN_Stack:
process( Clk)
begin
if rising_edge( Clk) then
case S is
When "00" => Null;
When "01" => Q3<=Q2; Q2<=Q1; Q1<=Q0; Q0<=T;
When "10" => Q0<=Q1; Q1<=Q2; Q2<=Q3; Q3<=B;
When "11" => Q0<=D; Q1<=Q2; Q2<=Q3; Q3<=B;
When others => Null;
end case;
end if;
end process;

ALU_process:
process( S3S2S1S0, Q1, Q0)
begin
case S3S2S1S0 is
when "0001" => D <= Q1+Q0;
when "0010" => D <= Q1-Q0;
when "0100" => D <= Q1(3 downto 0) * Q0(3 downto 0);
-- When "1000" => D <= Q1/Q0; -- This one tricky - make a ROM
when "1111" => D <= Q1 xor Q0;
when others => D <= (others=>'0');
end case;
end process;
end Behavioral;

Could anyone lend a helpful hand of suggesting me to related link regarding coding for simple calculator?

hi.. im really desperate because i have this project to submit this coming monday. it may be easy for you... a calculator... a simple one to be exact. i really have no idea how to start and if it's possible to be 8-bit.. to be honest.. i only have background in other software for antenna,microwave... so can you help me please?

I am sorry, but I don't help students who can't do their homework with such simple problems.

susheelcpanguluri

### susheelcpanguluri

Points: 2
haha...simple??...maybe for you but not for us...what if i'm asking you to design a bow tie antenna with three feeders using ADS or perhaps CST software can you really do it then??...ifyou can, then a big applause to you...coding or programming is actually not really related to my field..but unfortunately we have to take this subject because its in the silibus....never mind then if you won't help me out..thanks for your kindness...

f you are a engineering student, you follow the school plan, if you are smart enough to design a bow tie antenna, then writing a simple calculator should be a piece of cake, and for that matter, that does not grant you to SPAM this whole group with 20 or so copies of the same message, it only shows a disrespect and arrogance.

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